Francois Atallah

According to our database, Francois Atallah authored at least 10 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction.

Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors.

Francois Atallah, Keith A. Bowman, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory.

Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2017

Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage.

Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury

Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range.

Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine

IEEE J. Solid State Circuits, 2016

Adaptive power gating of 32-bit Kogge Stone adder.

Alexander E. Shapiro, Francois Atallah, Kyugseok Kim, Jihoon Jeong, Jeff Fischer, Eby G. Friedman

Integr., 2016

2015

8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range.

Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells.

Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors.

Keith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine

Proceedings of the 2014 International Test Conference, 2014

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.

Alex Park, Venkat Narayanan, Keith A. Bowman, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014