François Anceau

According to our database, François Anceau authored at least 15 papers between 1974 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Synchronized Interconnected ADPLLs for Distributed Clock Generation in 65 nm CMOS Technology.

Dimitri Galayko, Chuan Shan, Eldar Zianbetov, Mohammad Javidan, Anton Korniienko, François Anceau, Olivier Billoint, Éric Colinet, Elena Blokhina, Jérôme Juillard

IEEE Trans. Circuits Syst. II Express Briefs, 2019

2015

A distributed synchronization of all-digital PLLs network for clock generation in synchronous SOCs.

Chuan Shan, Eldar Zianbetov, François Anceau, Olivier Billoint, Dimitri Galayko

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014

A reconfigurable distributed architecture for clock generation in large many-core SoC.

Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

"Swimming pool"-like distributed architecture for clock generation in large many-core SoC.

Chuan Shan, François Anceau, Dimitri Galayko, Eldar Zianbetov

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Complexity in heterogeneous systems on chips: Dsign and analysis challenges.

Dimitri Galayko, Elena Blokhina, Eldar Zianbetov, Andrii Dudka, François Anceau, Éric Colinet, Anton Korniienko, Jérôme Juillard, Philippe Basset

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

FPGA prototyping of large reconfigurable ADPLL network for distributed clock generation.

Chuan Shan, Eldar Zianbetov, Weiqiang Yu, François Anceau, Olivier Billoint, Dimitri Galayko

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

On-chip clock error characterization for clock distribution system.

Chuan Shan, Dimitri Galayko, François Anceau

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Distributed clock generator for synchronous SoC using ADPLL network.

Eldar Zianbetov, Dimitri Galayko, François Anceau, Mohammad Javidan, Chuan Shan, Olivier Billoint, Anton Korniienko, Éric Colinet, Gérard Scorletti, J. M. Akrea, Jérôme Juillard

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Design and Modeling of ADPLL with sliding-window for wide range frequency tracking.

Chuan Shan, Dimitri Galayko, François Anceau

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

A Digitally Controlled Oscillator in a 65-nm CMOS process for SoC clock generation.

Eldar Zianbetov, François Anceau, Mohammad Javidan, Dimitri Galayko, Éric Colinet, Jérôme Juillard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

All-digital PLL array provides reliable distributed clock for SOCs.

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Anton Korniienko, Éric Colinet, Gérard Scorletti, Jean-Michel Akre, Jérôme Juillard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel technique to reduce the metastability of Bang-Bang Phase Frequency Detectors.

Mohammad Javidan, Eldar Zianbetov, François Anceau, Dimitri Galayko, Éric Colinet, Jérôme Juillard

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

FPGA implementation of reconfigurable ADPLL network for distributed clock generation.

Chuan Shan, Eldar Zianbetov, Mohammad Javidan, François Anceau, Mehdi Terosiet, Sylvain Feruglio, Dimitri Galayko, Olivier Romain, Éric Colinet, Jérôme Juillard

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

1989

Formal Verification: A Significant Step Towards Zero Deffect VLSI Design.

François Anceau

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

1974

Contribution à l'étude de systèmes hiérarchisés de ressources dans l'architecture des machines informatiques.

François Anceau

PhD thesis, 1974