François Abel

Orcid: 0000-0002-3295-0292

Affiliations:
  • IBM Research Zurich, Switzerland


According to our database1, François Abel authored at least 30 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
Automated parallel execution of distributed task graphs with FPGA clusters.
Future Gener. Comput. Syst., 2024

2023
Advancing Compilation of DNNs for FPGAs Using Operation Set Architectures.
IEEE Comput. Archit. Lett., 2023

DOSA: Organic Compilation for Neural Network Inference on Distributed FPGAs.
Proceedings of the IEEE International Conference on Edge Computing and Communications, 2023

Composability of Cloud Accelerators in Virtual World Simulations.
Proceedings of the 16th IEEE International Conference on Cloud Computing, 2023

2022
OmpSs@cloudFPGA: An FPGA Task-Based Programming Model with Message Passing.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

2021
A Case for Function-as-a-Service with Disaggregated FPGAs.
Proceedings of the 14th IEEE International Conference on Cloud Computing, 2021

Acceleration-as-a-µService: A Cloud-native Monte-Carlo Option Pricing Engine on CPUs, GPUs and Disaggregated FPGAs.
Proceedings of the 14th IEEE International Conference on Cloud Computing, 2021

2020
Programming Reconfigurable Heterogeneous Computing Clusters Using MPI With Transpilation.
Proceedings of the 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing, 2020

ZRLMPI: A Unified Programming Model for Reconfigurable Heterogeneous Computing Clusters.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
System Architecture for Network-Attached FPGAs in the Cloud using Partial Reconfiguration.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2017
An FPGA Platform for Hyperscalers.
Proceedings of the 25th IEEE Annual Symposium on High-Performance Interconnects, 2017

Microserver + micro-switch = micro-datacenter.
Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, 2017

2016
Network-attached FPGAs for data center applications.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Disaggregated FPGAs: Network Performance Comparison against Bare-Metal Servers, Virtual Machines and Linux Containers.
Proceedings of the 2016 IEEE International Conference on Cloud Computing Technology and Science, 2016

2015
Enabling FPGAs in Hyperscale Data Centers.
Proceedings of the 2015 IEEE 12th Intl Conf on Ubiquitous Intelligence and Computing and 2015 IEEE 12th Intl Conf on Autonomic and Trusted Computing and 2015 IEEE 15th Intl Conf on Scalable Computing and Communications and Its Associated Workshops (UIC-ATC-ScalCom), 2015

2014
On the Cost of Tunnel Endpoint Processing in Overlay Virtual Networks.
Proceedings of the 7th IEEE/ACM International Conference on Utility and Cloud Computing, 2014

2013
On the effect of mobile phone on migrant remittances: A closer look at international transfers.
Electron. Commer. Res. Appl., 2013

2012
Rx Stack Accelerator for 10 GbE Integrated NIC.
Proceedings of the IEEE 20th Annual Symposium on High-Performance Interconnects, 2012

2008
Lightspeed Communications in Supercomputers.
ERCIM News, 2008

2007
Design issues in next-generation merchant switch fabrics.
IEEE/ACM Trans. Netw., 2007

2006
Designing a Crossbar Scheduler for HPC Applications.
IEEE Micro, 2006

2005
Reliable control protocol for crossbar arbitration.
IEEE Commun. Lett., 2005

Control Path Implementation for a Low-Latency Optical HPC Switch.
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005

2004
Low-latency pipelined crossbar arbitration.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2003
10 A Four-Terabit Packet Switch Supporting Long Round-Trip Times.
IEEE Micro, 2003

Stability degree of switches with finite buffers and non-negligible round-trip time.
Microprocess. Microsystems, 2003

Current issues in packet switch design.
Comput. Commun. Rev., 2003

2002
Stability of CIOQ switches with finite buffers and non-negligible round-trip time.
Proceedings of the 11th International Conference on Computer Communications and Networks, 2002

A Four-Terabit Single-Stage Packet Switch with Large Round-Trip Time Support.
Proceedings of the 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21, 2002

2001
Optimized architecture and design of an output-queued CMOS switch chip.
Proceedings of the 10th International Conference on Computer Communications and Networks, 2001


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