Franco Maloberti

Orcid: 0000-0001-8596-7824

According to our database1, Franco Maloberti authored at least 310 papers between 1988 and 2024.

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Awards

IEEE Fellow

IEEE Fellow 1996, "For contributions to design methodologies for analog integrated circuits and outstanding leadership in microelectronics education and research.".

Timeline

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Bibliography

2024
A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
An Implantable Wireless System for Remote Hemodynamic Monitoring of Heart Failure Patients.
IEEE Trans. Biomed. Circuits Syst., August, 2023

A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A Hybrid Single-Inductor Bipolar Triple-Output DC-DC Converter With High-Quality Positive Outputs for AMOLED Displays.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Design of Phase-Interpolator Based Open-Loop Fractional Output Dividers.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

A low power 1.25fJ/conv-step 12-bit SAR ADC with a high-efficient Dynamic Comparator.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022
An Analog Multiplier Controlled Buck-Boost Converter.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Incremental-ΔΣ ADC With 106-dB DR for Reconfigurable Class-D Audio Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Overcoming the Transimpedance Limit: A Tutorial on Design of Low-Noise TIA.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

An Energy-Efficient Bridge-to-Digital Converter for Implantable Pressure Monitoring Systems.
IEEE Trans. Biomed. Circuits Syst., 2022

A Sub-0.25-pJ/bit 47.6-to-58.8-Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, 2022

Linearity Analysis of BiCMOS Coherent TIAs.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

A 10.8-to-37.4Gb/s Single-Loop Quarter-Rate BBCDR Without External Reference and Separate FD Featuring a Wide-Frequency-Acquisition Scheme.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Design Strategies for High-resolution High-speed Flash-assisted Pipelined SAR ADCs.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
A Hybrid Single-Inductor Bipolar-Output DC-DC Converter With Floating Negative Output for AMOLED Displays.
IEEE J. Solid State Circuits, 2021

A Time-Interleaved 2<sup>nd</sup>-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation.
IEEE J. Solid State Circuits, 2021

A Rail-to-Rail CMOS Voltage Comparator with Programmable Hysteresis.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

A 0.4 nJ Excitation Energy Bridge-to-Digital Converter for Implantable Pulmonary Artery Pressure Monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020
A SAR-ADC-Assisted DC-DC Buck Converter With Fast Transient Recovery.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration.
IEEE Trans. Circuits Syst., 2020

Order Statistics and Optimal Selection of Unit Elements in DACs to Enhance the Static Linearity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

A 170.7-dB FoM-DR 0.45/0.6-V Inverter-Based Continuous-Time Sigma-Delta Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2<sup>nd</sup>-Order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Multi-Bit Incremental Converters with Optimal Power Consumption and Mismatch Error.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Innovative Engineering Education in Circuits & Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

On the Design of High Switching Frequency DC-DC Buck Converter Power Stages for Automotive Post-Regulated Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Power-Efficient Hybrid Single-Inductor Bipolar-Output DC-DC Converter with Floating Negative Output for AMOLED Displays.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

Wireless Power Transfer and Data Communication for Intracranial Neural Recording Applications
Springer, ISBN: 978-3-030-40825-1, 2020

2019
Design of KY Converter With Constant On-Time Control Under DCM Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

An 86% Efficiency, Wide-V <sub>in</sub> SIMO DC-DC Converter Embedded in a Car-Radio IC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Guest Editorial Special Issue on the 2019 ISICAS: A CAS Journal Track Symposium.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Analysis of Parasitic Effects in Filamentary-Switching Memristive Memories Using an Approximated Verilog-A Memristor Model.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 550- $\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS.
IEEE J. Solid State Circuits, 2019

An Integrated DC-DC Converter With Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery.
IEEE J. Solid State Circuits, 2019

A CMOS Frequency Doubler from the Analog Cosine Mapping Function.
Circuits Syst. Signal Process., 2019

A Behavioral Model for Solar Cells With Transient Irradiation and Temperature Assessment.
IEEE Access, 2019

A 5-Bit 10-GS/sec Flash ADC with Resolution Enhancement using Metastability Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Study of DAC Architectures for Integrated Laser Driver Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A Voltage-Time Model for Memristive Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A 220-MHz Bondwire-Based Fully-Integrated KY Converter With Fast Transient Response Under DCM Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Area and Power Efficient Ultra-Wideband Transmitter Based on Active Inductor.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Guest Editorial Special Issue on the 2018 ISICAS: A CAS Journal Track Symposium.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Nano-Ampere Low-Dropout Regulator Designs for IoT Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Capacitance Super Multiplier for Sub-Hertz Low-Pass Integrated Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 10-MHz Bandwidth Two-Path Third-Order ΣΔ Modulator With Cross-Coupling Branches.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Remotely-powered front-end at 2.45 GHz for real-time continuous temperature sensing.
Proceedings of the 2018 IEEE International Conference on RFID, 2018

Design of a SIBO DC-DC Converter for AMOLED Display Driving.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

High-resolution ADCs design in sensors.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

An 86% efficiency SIMO DC-DC converter with one boost, one buck, and a floating output voltage for car-radio.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Design Considerations for Integrated, High-Voltage DC-DC Converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Approximated Verilog-A Model for Memristive Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High Linearity SAR ADC for High Performance Sensor System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Timing Skew Calibration Method for Time-Interleaved FATI ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

All Wireless, 16-Channel Epilepsy Control System with Sub-µW/Channel and Closed-Loop Stimulation Using a Switched-Capacitor-Based Active Charge Balancing Method.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

High-Resolution Time-Interleaved Eight-Channel ADC for Li-Ion Battery Stacks.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

High-Resolution SAR ADC With Enhanced Linearity.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 0.4-V Supply Curvature-Corrected Reference Generator With 84.5-ppm/°C Average Temperature Coefficient Within -40 °C to 130 °C.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Handheld High-Sensitivity Micro-NMR CMOS Platform With B-Field Stabilization for Multi-Type Biological/Chemical Assays.
IEEE J. Solid State Circuits, 2017

Feasibility Study of an Ultra High Speed Current-Mode SAR ADC.
Proceedings of the New Generation of CAS, 2017

A Cross-Coupled Redundant Sense Amplifier for Radiation Hardened SRAMs.
Proceedings of the New Generation of CAS, 2017

A 10-Bit Radiation-Hardened by Design (RHBD) SAR ADC for Space Applications.
Proceedings of the New Generation of CAS, 2017

Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC.
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

A high-speed level shifting technique and its application in high-voltage, synchronous DC-DC converters with quasi-ZVS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

High resolution and linearity enhanced SAR ADC for wearable sensing systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A low-power low-noise CMOS voltage reference with improved PSR for wearable sensor systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power/data platform for high data rate in implanted neural monitoring system.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

Keynote speech: Data converters for mobile and autonomous applications.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
A 10-b 200-kS/s 250-nA Self-Clocked Coarse-Fine SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Continuos Time ΣΔ modulator with efficient gain compensated integrators.
Microelectron. J., 2016

A Time-Interleaved Ring-VCO with Reduced 1/f<sup>3</sup> Phase Noise Corner, Extended Tuning Range and Inherent Divided Output.
IEEE J. Solid State Circuits, 2016

A capacitive sensor interface for high-resolution acquisitions in hostile environments.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Very-low-voltage and ultra-low-power analog circuits for nomadic applications.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2.7 A 0.003mm2 1.7-to-3.5GHz dual-mode time-interleaved ring-VCO achieving 90-to-150kHz 1/f3 phase-noise corner.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

28.1 A handheld 50pM-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Optimization of the data rate of an OOK CMOS medical transmitter based on LC oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A pipeline ADC for very high conversion rates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Design of resistive non-volatile memories for rad-hard applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Mismatch and parasitics limits in capacitors-based SAR ADCs.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

An integrated rad-hard test-vehicle for embedded emerging memories.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Design of a compact and low supply voltage CMOS voltage reference generator.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

An 8-bit 0.7-GS/s single channel flash-SAR ADC in 65-nm CMOS technology.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A CMOS Current-Mode Magnetic Hall Sensor With Integrated Front-End.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Remotely Powered Implantable Biomedical System With Location Detector.
IEEE Trans. Biomed. Circuits Syst., 2015

Voltage reference architectures for low-supply-voltage low-power applications.
Microelectron. J., 2015

A 0.02 mm<sup>2</sup> 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad.
IEEE J. Solid State Circuits, 2015

Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate.
IEEE J. Solid State Circuits, 2015

Corrections to "A 0.02 mm<sup>2</sup> 59.2 dB SFDR 4th-Order SC LPF With 0.5-to-10 MHz Bandwidth Scalability Exploiting a Recycling SC-Buffer Biquad".
IEEE J. Solid State Circuits, 2015

Polyphase Decomposition for Tunable Band-Pass Sigma-Delta A/D Converters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

On the design of incremental data converters with extended range.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A split transconductor high-speed SAR ADC.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A single Op-Amp 0+2 sigma-delta modulator.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of a low power time to digital converter for flow metering applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Design of an op-amp free voltage reference with PWM regulation.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Split-SAR ADCs: Improved Linearity With Power and Speed Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A low-power PPM demodulator for remotely powered batteryless implantable devices.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

17.2 A 0.0013mm<sup>2</sup> 3.6μW nested-current-mirror single-stage amplifier driving 0.15-to-15nF capacitive loads with >62° phase margin.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 2+1 multi-bit incremental architecture using Smart-DEM algorithm.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A current-mode CMOS integrated microsystem for current spinning magnetic hall sensors.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Sampled-data operational-amplifier with ultra-low supply voltage and sub µW power consumption.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 490-nA, 43-ppm/°C, sub-0.8-V supply voltage reference.
Proceedings of the ESSCIRC 2014, 2014

Remote powering platform for implantable sensor systems at 2.45 GHz.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Servo-controlled remote powering and low-power data communication of implantable bio-systems for freely moving animals.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013
A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013

High-Q adaptive matching network for remote powering of UHF RFIDs and wireless sensor systems.
Proceedings of the IEEE Topical Conference on Wireless Sensors and Sensor Networks, 2013

Two-Path Quadrature Cascaded Band-Pass Sigma-Delta Modulators.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Short range remote powering of implanted electronics for freely moving animals.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Far-field UHF remotely powered front-end for patient monitoring with wearable antenna.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Remotely powered implantable heart monitoring system for freely moving animals.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

A 1.96-mW, 2.6-MHz bandwidth discrete time quadrature band-pass ΣΔ modulator.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High-order multi-bit incremental converter with Smart-DEM algorithm.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design of a third-order ΣΔ modulator with minimum op-amps output swing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Design and comparison of class-C and class-D power amplifiers for remotely powered systems.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

A 105-dB SNDR, 10 kSps multi-level second-order incremental converter with smart-DEM consuming 280 µW and 3.3-V supply.
Proceedings of the ESSCIRC 2013, 2013

2012
Fractional Frequency Synthesizers With Low Order Time-Variant Digital Sigma-Delta Modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Hardware Reduction in Digital Delta-Sigma Modulators via Bus-Splitting and Error Masking - Part II: Non-Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation.
IEEE J. Solid State Circuits, 2012

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC.
IEEE J. Solid State Circuits, 2012

A 88-dB DR, 84-dB SNDR Very Low-Power Single Op-Amp Third-Order Σ Δ Modulator.
IEEE J. Solid State Circuits, 2012

Performance enhanced op-amp for 65nm CMOS technologies and below.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Interference rejection in delay line based quadrature band-pass ΣΔ modulators.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Intelligent cage for remotely powered freely moving animal telemetry systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Simulation oriented rectenna design methodology for remote powering of wireless sensor systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 1-V 1.1-MHz BW digitally assisted multi-bit multi-rate hybrid CT ΣΔ with 78-dB SFDR.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

An incremental ADC sensor interface with input switch-Less integrator featuring 220-nVrms resolution with ±30-mV input range.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Remotely powered telemetry system with dynamic power-adaptation for freely moving animals.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

2011
A Pseudorandom Number Generator Based on Time-Variant Recursion of Accumulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Hardware Reduction in Digital Delta-Sigma Modulators Via Bus-Splitting and Error Masking - Part I: Constant Input.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 0.024mm<sup>2</sup> 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 84dB SNDR 100kHz bandwidth low-power single op-amp third-order ΔΣ modulator consuming 140μW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A low-power third-order ΔΣ modulator using a single operational amplifier.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Use of time variant digital sigma-delta for fractional frequency synthesizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A novel implementation of dithered digital delta-sigma modulators via bus-splitting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An analog readout circuit with offset calibration for cantiliver-based DNA detection.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Digital assisted high-order multi-bit analog to digital ramp converters.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Efficient Dithering in MASH Sigma-Delta Modulators for Fractional Frequency Synthesizers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS.
IEEE J. Solid State Circuits, 2010

A Micropower Chopper - CDS Operational Amplifier.
IEEE J. Solid State Circuits, 2010

A micropower chopper-correlated double-sampling amplifier with 2µV standard deviation offset and 37nV/√Hz input noise density.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Double-sampling analog-look-ahead second order ΣΔ modulator with reduced dynamics.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Digitally assisted multi-Bit ΣΔ modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of a 70-MHz IF 10-MHz bandwidth bandpass ΣΔ modulator for WCDMA applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An all-digital PLL with a first order noise shaping Time-to-Digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low-power ripple-free chopper amplifier with correlated double sampling de-chopping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Multi-rate segmented time-interleaved current steering DAC with unity-elements sharing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A two op-amps third-order ΣΔ modulator with complex conjugate NTF zeros.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Pseudorandom sequence generation for mismatch analog compensation of ADCs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

First Order Noise Shaping Local-Oscillator Based Time-to-Digital Converter.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Time-domain equivalent design of continuous-time ΣΔ modulators.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Comments on "Efficient Multibit Quantization in Continuous-Time Sigma Delta Modulators".
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Wideband Sigma-Delta Modulator With Cross-Coupled Two-Paths.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at -0.12 dB From Full Scale Input.
IEEE J. Solid State Circuits, 2009

Slew-rate and Gain Enhancement in Two Stage Operational Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Complex Cascaded Bandpass SigmaDelta ADC Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An Anti-aliasing Multi-rate SigmaDelta Modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Optimum selection of capacitive array for multibit Sigma-Delta modulators without DEM.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

High efficiency DC-DC buck converter with 60/120-MHz switching frequency and 1-A output current.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Multi-bit high-order incremental converters with digital calibration.
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008
A Clock-Less 10-bit Pipeline-Like A/D Converter for Self-Triggered Sensors.
IEEE J. Solid State Circuits, 2008

40 MHz IF 1 MHz Bandwidth Two-Path Bandpass ΣΔ Modulator With 72 dB DR Consuming 16 mW.
IEEE J. Solid State Circuits, 2008

A 4-Output Single-Inductor DC-DC Buck Converter with Self-Boosted Switch Drivers and 1.2A Total Output Current.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Digitally-enhanced 2nd-order DeltaSigma modulator with unity-gain signal transfer function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Band-pass SigmaDelta architectures with single and two parallel paths.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A Wide-band 2-path cross-coupled sigma delta ADC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

On the design of single-inductor multiple-output DC-DC buck converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Design of an ultra-low power SA-ADC with medium/high resolution and speed.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Automatic impedance control for chip-to-chip interconnections.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Digitally-enhanced high-order ΔΣ modulators.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Use of chopper-notch modulator in chopper amplifiers for replica images cancellation.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A two-bit-per-cycle successive-approximation ADC with background offset calibration.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

On the design of single-inductor double-output DC-DC buck, boost and buck-boost converters.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Third-order ΣΔ modulator with 61-dB SNR and 6-MHz bandwidth consuming 6 mW.
Proceedings of the ESSCIRC 2008, 2008

On the design of band-pass quadrature ΣΔ modulators.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

High-performance data converters: Trends, process technologies and design challenges.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Cancellation of Amplifier Offset and 1/f Noise: An Improved Chopper Stabilized Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Power-Efficient Two-Channel Time-Interleaved ΣΔ Modulator for Broadband Applications.
IEEE J. Solid State Circuits, 2007

A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

86 dB DR Cross-Coupled Time-Interleaved xx ADC for Audio Signal Band with 322 µA Current Consumption.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power Sinc3 Filter for Sigma-Delta Modulators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Noise-Coupled Multi-Cell Delta-Sigma ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Multi-Bit Sigma Delta ADC with Reduced Feedback Levels, Extended Dynamic Range and Increased Tolerance for Analog Imperfections.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Switch Bootstrapping for Precise Sampling Beyond Supply Voltage.
IEEE J. Solid State Circuits, 2006

A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10-bit pipeline A/D converter without timing signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Digital scheme for quantizer and integrator swing reduction in multibit sigma-delta modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low-power 6-bit flash ADC for high-speed data converters architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On-line calibration of offset and gain mismatch in time-interleaved ADC using a sampled-data chaotic bit-stream.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Delta-Sigma Modulators for Power-Efficient A/D Conversion in High-Speed Wireless Communications.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Dynamic Element Matching for Low-power ΣΔModulator with R-C based internal DAC.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Improved Chopper Stabilized Amplifier for Offset and 1/f Noise Cancellation.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2005
SC amplifier and SC integrator with an accurate gain of 2.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A low-power multi-bit ΣΔ modulator in 90-nm digital CMOS without DEM.
IEEE J. Solid State Circuits, 2005

A low-power digital PWM DC/DC converter based on passive sigma-delta modulator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Improved modeling of sigma-delta modulator non-idealities in Simulink.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Heap charge pump optimisation by a tapered architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Symbolic small-signal analysis (SSA) tool.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

High-efficiency power amplifier for wireless sensor networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Behavioral model of magnetic sensors for SPICE simulations.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Design of ultra low-power analog cells with dynamic current biasing.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

Non-linear behavioral model of a bipolar track and hold amplifier for high-speed and high-resolution ADCs.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A PWM dual-output DC/DC boost converter in a 0.13μm CMOS technology for cellularphone backlight application.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Design of ΣΔ modulators with reduced number of operational amplifiers.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Use of non-linear Chua's circuit for on-line offset calibration of ADC.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Fractional-N PLL with 90° phase shift lock and active switched-capacitor loop filter.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A low noise, high power supply rejection low dropout regulator for wireless system-on-chip applications.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

A bootstrapped switch for precise sampling of inputs with signal range beyond supply voltage.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2004
A fourth-order single-bit switched-capacitor Σ-Δ modulator for distributed sensor applications.
IEEE Trans. Instrum. Meas., 2004

Time-interleaved sigma-delta modulator using output prediction scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Online calibration of a Nyquist-rate analog-to-digital converter using output code-density histograms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

2.45 GHz power and data transmission for a low-power autonomous sensors platform.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

X ray and blue print: tools for MOSFET analog circuit design addressing short-channel effects.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A 0.18µm CMOS SC lowpass filter for Bluetooth channel selection.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Domino free 4-path time-interleaved second order sigma-delta modulator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Op-amp swing reduction in sigma-delta modulators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Feed-forward path and gain-scaling - a swing and distortion reduction scheme for second order sigma-delta modulator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Digital background auto-calibration of DAC non-linearity in pipelined ADCs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Use of dynamic element matching in a multi-path sigma-delta modulator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A high speed and low power CMOS current comparator for photon counting systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Novel Design Methodology for Short-Channel MOSFET Analog Circuits.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Phase noise improvement in fractional-N synthesizer with 90° phase shift lock.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Gain and offset mismatch calibration in multi-path sigma-delta modulators.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

CAD system for design and simulation of data converters.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An 8-bit current mode ripple folding A/D converter.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A particle detector fully-programmable interface circuit for satellite applications.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Mega-Mesh sensor network design.
Proceedings of the 2003 IEEE International Geoscience and Remote Sensing Symposium, 2003

2002
On the design of low-voltage, low-power CMOS analog multipliers for RF applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002

An improved bandgap reference with high power supply rejection.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Design of oversampling current steering DAC with 640 MHz equivalent clock frequency.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulator.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Dynamic stage matching for parallel pipeline A/D converters.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Very high-speed BJT buffer for track-and-hold amplifiers with enhanced linearity.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Pipeline of successive approximation converters with optimum power merit factor.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications.
Proceedings of the 2002 Design, 2002

2001
Curvature-compensated BiCMOS bandgap with 1-V supply voltage.
IEEE J. Solid State Circuits, 2001

Design considerations for band-pass sigma delta modulators.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Optimization of the integrator output swing in low-voltage sigma-delta modulators.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A feedforward compensation scheme for high gain wideband amplifiers.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A comparative study of digital ΣΔ modulators for fractional-N synthesis.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

On-line digital correction of the harmonic distortion in analog-to-digital converters.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A 1.8 GHz CMOS low-noise amplifier.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A 900 MHz, 0.9 V low-power CMOS downconversion mixer.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

2000
An integrated microsystem for 3-D magnetic field measurements.
IEEE Trans. Instrum. Meas., 2000

A low-voltage CMOS multiplier for RF applications (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

A multipath polyphase digital-to-analog converter for software radio transmission systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Periodical nonuniform individually sampled switched-capacitor circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A low-voltage CMOS multiplier and its application to a 900 MHz RF downconversion mixer.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
An 0.8-μm CMOS mixed analog-digital integrated audiometric system.
IEEE J. Solid State Circuits, 1999

A fully integrated CMOS magnetic current monitor.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High resolution rail-to-rail ADC in CMOS digital technology.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

High-performance BiCMOS output buffer design strategies.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Modeling sigma-delta modulator non-idealities in SIMULINK(R).
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Switched-capacitor Litton-code matched filter for satellite ODBH bus.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low-voltage switched-capacitor circuits.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A 1 V second order sigma-delta modulator.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A low voltage high resolution pipelined incremental ADC.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Signal Processing for Smart Sensors.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

An high-swing, 1.8 V, push-pull opamp for sigma-delta modulators.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

The Chinese Abacus Method: Can We Use It for Digital Arithmetic?
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
Programmable time-multiplexed switched-capacitor variable equalizer for arbitrary frequency response realizations.
IEEE J. Solid State Circuits, 1997

1996
Two-dimensional magnetic microsensor with on-chip signal processing for contactless angle measurement.
IEEE J. Solid State Circuits, 1996

VERDI: an acoustically programmable and adjustable CMOS mixed-mode signal processor for hearing aid applications.
IEEE J. Solid State Circuits, 1996

Analog-to-digital converters for optical sensor arrays.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Power consumption optimization of 8 bit, 2 MHz voltage scaling subranging CMOS 0.5 μm DAC.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Research and innovation: a new route to development.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

ALCD-analog libraries on CMOS digital process.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A 200-MHz crystal oscillator with 0.5 ppm long term stability.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995
A single-chip optical sensor with analog memory for motion detection.
IEEE J. Solid State Circuits, July, 1995

An Analog High-Speed Wide-Range Programmable Monostable Multivibrator.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

High Dynamic Range Interface System for a Micromachined Integrated AC-Power Sensor.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An Incremental A/C Converter for Accurate Vector Probe Measurements.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Class of Fully-Differential Basic Building Blocks Based on Unity-Gain Differnence Feedback.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Novel Circuit Solutions for Rail-to-Rail CMOS Buffer.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
High-speed, low-switching noise CMOS memory data output buffer.
IEEE J. Solid State Circuits, November, 1994

Smart sensor interface with A/D conversion and programmable calibration.
IEEE J. Solid State Circuits, August, 1994

Sinewave modulation for data communication by direct digital synthesis and sigma delta techniques.
Eur. Trans. Telecommun., 1994

Switched Capacitor Dual-Collector Magnetotransistors.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Design of High Accuracy Video Comparator.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Gain Enhancement Technique for High-Speed Switched-Capacitor Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
TOSCA: a simulator for switched-capacitor noise-shaping A/D converters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Multiplier-free Lagrange interpolators for oversampled D/A converters.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Active Compensation of Parasitic Capacitances for Very High Frequency CMOS DACs.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


1992
ASIC-based acoustic echo-canceller board for VME bus.
Eur. Trans. Telecommun., 1992

1991
An oversampling-based DTMF generator.
IEEE Trans. Commun., 1991

A direct-digital synthesizer with improved spectral performance.
IEEE Trans. Commun., 1991

Design and verification of A CMOS transconductance cell with extended linearity.
Eur. Trans. Telecommun., 1991

1990
Custom integrated circuits for audio processing and signalling in vehicular units.
Eur. Trans. Telecommun., 1990

1989
A 100-MHz CMOS DAC for video-graphic systems.
IEEE J. Solid State Circuits, June, 1989

1988
A tunable switched-capacitor programmable N-path tone receiver and generator.
IEEE J. Solid State Circuits, December, 1988


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