Franck Julien

According to our database1, Franck Julien authored at least 9 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Notched gate MOSFET for capacitance reduction in RF SOI technology.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2022
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Schmitt trigger to benchmark the performance of a new zero-cost transistor.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology.
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2015
Dynamic current reduction of CMOS digital circuits through design and process optimization.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Layout optimizations to decrease internal power and area in digital CMOS standard cells.
Proceedings of the 38th International Convention on Information and Communication Technology, 2015

2014
Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2011
Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress.
Microelectron. Reliab., 2011

Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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