Francisco Veirano

Orcid: 0000-0001-6721-1855

According to our database1, Francisco Veirano authored at least 15 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Low Output Voltage Closed-Loop Current Source for Neural Stimulation.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Low-Power Wireless Sensor Network for Real-Time Indoor Air Quality Monitoring with CO2 Sensors.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
Trends in Volumetric-Energy Efficiency of Implantable Neurostimulators: A Review From a Circuits and Systems Perspective.
IEEE Trans. Biomed. Circuits Syst., February, 2023

2022
A Compact Lithium-Ion Battery Charger for Low-Power Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Near threshold pulse transit time processor for central blood pressure estimation.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

2019
Optimal asymmetrical back plane biasing for energy efficient digital circuits in 28 nm UTBB FD-SOI.
Integr., 2019

2018
Gate drive losses reduction in switched-capacitor DC-DC converters.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
Optimum nMOS/pMOS Imbalance for Energy Efficient Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A Low Cost System for Self Measurements of Power Consumption in Field Programmable Gate Arrays.
J. Low Power Electron., 2017

Asymmetrical length biasing for energy efficient digital circuits.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
General Top/Bottom-Plate Charge Recycling Technique for Integrated Switched Capacitor DC-DC Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Minimum Operating Voltage Due to Intrinsic Noise in Subthreshold Digital Logic in Nanoscale CMOS.
J. Low Power Electron., 2016

Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOI.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

2015
High slew-rate OTA with low quiescent current based on non-linear current mirror.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2013
Ultra low power pulse generator based on a ring oscillator with direct path current avoidance.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013


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