Francisco Triviño

According to our database1, Francisco Triviño authored at least 11 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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PhD thesis 
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Links

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Bibliography

2015
A Brief Comment on "A Complete Self-Testing and Self-Configuring NoC Infrastructure for Cost-Effective MPSoCs" [ACM Transactions on Embedded Computing Systems 12 (2013) Article 106].
ACM Trans. Embed. Comput. Syst., 2015

2013
A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
ACM Trans. Embed. Comput. Syst., 2013

Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms.
Proceedings of the 2013 International Symposium on System on Chip, 2013

A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs.
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, 2013

2012
Network-on-Chip virtualization in Chip-Multiprocessor Systems.
J. Syst. Archit., 2012

OSR-Lite: Fast and deadlock-free NoC reconfiguration framework.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Exploring NoC Virtualization Alternatives in CMPs.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

2011
Virtualizing network-on-chip resources in chip-multiprocessors.
Microprocess. Microsystems, 2011

NoC Reconfiguration for CMP Virtualization.
Proceedings of The Tenth IEEE International Symposium on Networking Computing and Applications, 2011

Self-related traces: An alternative to full-system simulation for NoCs.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

A fast centralized computation routing algorithm for self-configuring NoC systems.
Proceedings of the 18th International Conference on High Performance Computing, 2011


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