Francisco Tirado

Orcid: 0000-0003-0974-2687

According to our database1, Francisco Tirado authored at least 120 papers between 1977 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Preface to the CLTM-CLTD 2023 Special Issue.
CLEI Electron. J., 2024

2022
Optimization of a line detection algorithm for autonomous vehicles on a RISC-V with accelerator.
J. Comput. Sci. Technol., 2022

Performance Portability Assessment: Non-negative Matrix Factorization as a Case Study.
Proceedings of the Euro-Par 2022: Parallel Processing Workshops, 2022

Portability and Performance Assessment of the Non-Negative Matrix Factorization Algorithm with OpenMP and SYCL.
Proceedings of the XLVIII Latin American Computer Conference, 2022

2020
Leveraging knowledge-as-a-service (KaaS) for QoS-aware resource management in multi-user video transcoding.
J. Supercomput., 2020

2017
CEPRAM: Compression for Endurance in PCM RAM.
J. Circuits Syst. Comput., 2017

Energy Efficiency Optimization of Task-Parallel Codes on Asymmetric Architectures.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

2015
Write-Aware Replacement Policies for PCM-Based Systems.
Comput. J., 2015

Non-negative Matrix Factorization on Low-Power Architectures and Accelerators: A Comparative Study.
Comput. Electr. Eng., 2015

NMF-mGPU: non-negative matrix factorization on multi-GPU systems.
BMC Bioinform., 2015

System level exploration of a STT-MRAM based level 1 data-cache.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Improving Pelifo Cache Replacement Policy: Hardware Reduction and Thread-Aware Extension.
J. Circuits Syst. Comput., 2014

2013
Offset Printing Plate Quality Sensor on a Low-Cost Processor.
Sensors, 2013

Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials.
Integr., 2013

Robust motion estimation on a low-power multi-core DSP.
EURASIP J. Adv. Signal Process., 2013

Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor.
EURASIP J. Adv. Signal Process., 2013

Multi-GPU based on multicriteria optimization for motion estimation system.
EURASIP J. Adv. Signal Process., 2013

Design exploration of a NVM based hybrid instruction memory organization for embedded platforms.
Des. Autom. Embed. Syst., 2013

GPU-based acceleration of bio-inspired motion estimation model.
Concurr. Comput. Pract. Exp., 2013

Implementation of a Low-Cost Mobile Devices to Support Medical Diagnosis.
Comput. Math. Methods Medicine, 2013

Non-negative matrix factorization on low-power architectures: a comparative study.
Proceedings of the 20th European MPI Users's Group Meeting, 2013

Reducing writes in phase-change memory environments by using efficient cache replacement policies.
Proceedings of the Design, Automation and Test in Europe, 2013

Fault Tolerance on NoCs.
Proceedings of the 27th International Conference on Advanced Information Networking and Applications Workshops, 2013

2012
A Low Cost Matching Motion Estimation Sensor Based on the NIOS II Microprocessor.
Sensors, 2012

Reducing Cache Hierarchy Energy Consumption by Predicting Forwarding and Disabling Associative Sets.
J. Circuits Syst. Comput., 2012

eHR software, multinational corporations and emerging China: Exploring the role of information through a postcolonial lens.
Inf. Organ., 2012

2011
Hybrid timing-address oriented load-store queue filtering for an x86 architecture.
IET Comput. Digit. Tech., 2011

Parallelism on the Nonnegative Matrix Factorization.
Proceedings of the Applications, Tools and Techniques on the Road to Exascale Computing, Proceedings of the conference ParCo 2011, 31 August, 2011

Biclustering and classification analysis in gene expression using Nonnegative Matrix Factorization on multi-GPU systems.
Proceedings of the 11th International Conference on Intelligent Systems Design and Applications, 2011

2010
MARQ: an online tool to mine GEO for experiments with similar or opposite gene expression signatures.
Nucleic Acids Res., 2010

Stack filter: Reducing L1 data cache power consumption.
J. Syst. Archit., 2010

Not Just Software: Free Software and the (Techno) Political Action.
Int. J. Technoethics, 2010

On-Line Multi-Threaded Processing of Web User-Clicks on Multi-Core Processors.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2010, 2010

L1 Data Cache Power Reduction Using a Forwarding Predictor.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Building efficient multi-threaded search nodes.
Proceedings of the 19th ACM Conference on Information and Knowledge Management, 2010

2009
Replacing Associative Load Queues: A Timing-Centric Approach.
IEEE Trans. Computers, 2009

SENT: semantic features in text.
Nucleic Acids Res., 2009

GeneCodis: interpreting gene lists through enrichment analysis and integration of diverse biological information.
Nucleic Acids Res., 2009

Using age registers for a simple load-store queue filtering.
J. Syst. Archit., 2009

Endmember Extraction from Hyperspectral Imagery using a Parallel Ensemble Approach with Consensus Analysis.
Proceedings of the IEEE International Geoscience & Remote Sensing Symposium, 2009

Stack oriented data cache filtering.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Parallel Implementation of the 2D Discrete Wavelet Transform on Graphics Processing Units: Filter Bank versus Lifting.
IEEE Trans. Parallel Distributed Syst., 2008

bioNMF: a web-based tool for nonnegative matrix factorization in biology.
Nucleic Acids Res., 2008

GPU for Parallel On-Board Hyperspectral Image Processing.
Int. J. High Perform. Comput. Appl., 2008

Energy reduction of the fetch mechanism through dynamic adaptation.
IET Comput. Digit. Tech., 2008

Improving Search Engines Performance on Multithreading Processors.
Proceedings of the High Performance Computing for Computational Science, 2008

Applying speculation techniques to implement functional units.
Proceedings of the 26th International Conference on Computer Design, 2008

Exploiting Hybrid Parallelism in Web Search Engines.
Proceedings of the Euro-Par 2008, 2008

2007
Parallel Morphological Endmember Extraction Using Commodity Graphics Hardware.
IEEE Geosci. Remote. Sens. Lett., 2007

Efficient Object Placement including Node Selection in a Distributed Virtual Machine.
Proceedings of the Parallel Computing: Architectures, 2007

Multigrid Smoothers on Multicore Architectures.
Proceedings of the Parallel Computing: Architectures, 2007

2006
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Bit-Parallel Finite Field Multipliers for Irreducible Trinomials.
IEEE Trans. Computers, 2006

A Load-Store Queue Design Based on Predictive State Filtering.
J. Low Power Electron., 2006

bioNMF: a versatile tool for non-negative matrix factorization in biology.
BMC Bioinform., 2006

Biclustering of gene expression data by non-smooth non-negative matrix factorization.
BMC Bioinform., 2006

Enhancing the Performance of Multigrid Smoothers in Simultaneous Multithreading Architectures.
Proceedings of the High Performance Computing for Computational Science, 2006

DMDC: Delayed Memory Dependence Checking through Age-Based Filtering.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

2005
Cached Geometry Manager for View-dependent LOD Rendering.
Proceedings of the 13-th International Conference in Central Europe on Computer Graphics, 2005

Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2005

A Power-Efficient and Scalable Load-Store Queue Design.
Proceedings of the Integrated Circuit and System Design, 2005

Energy-aware fetch mechanism: trace cache and BTB customization.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism..
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Two-way clustering of gene expression profiles by sparse matrix factorization.
Proceedings of the Fourth International IEEE Computer Society Computational Systems Bioinformatics Conference Workshops & Poster Abstracts, 2005

Improving superword level parallelism support in modern compilers.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Exploiting Multilevel Parallelism Within Modern Microprocessors: DWT as a Case Study.
Proceedings of the High Performance Computing for Computational Science, 2004

Adaptive Tuning of Reserved Space in an Appel Collector.
Proceedings of the ECOOP 2004, 2004

Dynamic Management of Nursery Space Organization in Generational Collection.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004

2003
A parallel multigrid solver for viscous flows on anisotropic structured grids.
Parallel Comput., 2003

Customizing the Branch Predictor to Reduce Complexity and Energy Consumption.
IEEE Micro, 2003

Hybrid Parallelization of a Compact Genetic Algorithm.
Proceedings of the 11th Euromicro Workshop on Parallel, 2003

Branch prediction on demand: an energy-efficient solution.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Vectorization of Multigrid Codes Using SIMD ISA Extensions.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Vectorization of the 2D Wavelet Lifting Transform Using SIMD Extensions.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Analysis of simulation-adapted SPEC 2000 benchmarks.
SIGARCH Comput. Archit. News, 2002

Wavelet Transform for Large Scale Image Processing on Modern Microprocessors.
Proceedings of the High Performance Computing for Computational Science, 2002

Beowulf Performance in CFD Multigrid Applications.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

A Parallel Cloth Simulator Using Multilevel Algorithms.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Parallel Wavelet Transform for Large Scale Image Processing.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

-D Wavelet Transform Enhancement on General-Purpose Microprocessors: Memory Hierarchy and SIMD Parallelism Exploitation.
Proceedings of the High Performance Computing, 2002

2001
Analysing value substitution and confidence estimation for value prediction.
J. Syst. Archit., 2001

Parallel Multigrid for Anisotropic Elliptic Equations.
J. Parallel Distributed Comput., 2001

A Parallel Compact Genetic Algorithm for Multi-FPGA Partitioning.
Proceedings of the Ninth Euromicro Workshop on Parallel and Distributed Processing, 2001

A Multigrid Solver for the Incompressible Navier-Stokes Equations on a Beowulf-Class System.
Proceedings of the 2001 International Conference on Parallel Processing, 2001

2000
Data Locality Exploitation in the Decomposition of Regular Domain Problems.
IEEE Trans. Parallel Distributed Syst., 2000

Value Prediction as a Cost-Effective Solution to Improve Embedded Processors Performance.
Proceedings of the Vector and Parallel Processing, 2000

A robust multigrid solver on parallel computers.
Proceedings of the Eight Euromicro Workshop on Parallel and Distributed Processing, 2000

A Power Perspective of Value Speculation for Superscalar Microprocessors.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Impact of PE Mapping on Cray T3E Message-Passing Performance.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Power-Efficient Value Speculation for High-Performance Microprocessors.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
An environment to develop parallel code for solving partial differential equations based-problems.
J. Syst. Archit., 1999

Unified data path allocation and BIST intrusion.
Integr., 1999

A Parallel Robust Multigrid Algorithm Based on Semi-Coarsening.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1999

A Method for Model Parameter Identification Using Parallel Genetic Algorithms.
Proceedings of the Recent Advances in Parallel Virtual Machine and Message Passing Interface, 1999

Parallel resolution of alternating-line processes by means of pipelining techniques.
Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999

Solution of Alternating-Line Processes on Modern Parallel Computers.
Proceedings of the International Conference on Parallel Processing 1999, 1999

Message Passing Evaluation and Analysis on Cray T3E and SGI Origin 2000 Systems.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Implementation of Hybrid Context Based Value Predictors Using Value Sequence Classification.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1998
Partitioning Regular Domains on Modern Parallel Computers.
Proceedings of the Vector and Parallel Processing, 1998

A special-purpose parallel computer for solving partial differential equations.
Proceedings of the Sixth Euromicro Workshop on Parallel and Distributed Processing, 1998

Register Allocation with Simultaneous BIST Intrusio.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

1997
Relationships Between Efficiency and Execution Time of Full Multigrid Methods on Parallel Computers.
IEEE Trans. Parallel Distributed Syst., 1997

A SIMD computer for multigrid methods.
SIGARCH Comput. Archit. News, 1997

Automatic Generation of Parallel Code for Solving PDE Based Problems.
Proceedings of the IASTED International Conference on Parallel and Distributed Systems, 1997

1996
A method for area estimation of data-path in high level synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Some Aspects About the Scalability of Scientific Applications on Parallel Architectures.
Parallel Comput., 1996

Deblocking Event Algorithm: A New Approach to Conservative Parallel Discrete Event Simulation.
Proceedings of the 4th Euromicro Workshop on Parallel and Distributed Processing (PDP '96), 1996

1995
Distributed parallel computers versus PVM on a workstation cluster in the simulation of time dependent partial differential equations.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

1994
Numerical Aspects And Solution Of Some Nonlinear Scrodinger Systems On A Distributed Parallel Computer.
Proceedings of the Second Euromicro Workshop on Parallel and Distributed Processing, 1994

1993
RT-level synthesis.
Microprocess. Microprogramming, 1993

Data path structures and heuristics for testable allocation in high level synthesis.
Microprocess. Microprogramming, 1993

Guidance for optimization-based synthesis tools.
Microprocess. Microprogramming, 1993

An approach to module binding by fuzzy partitioning.
Proceedings of the European Design Automation Conference 1993, 1993

1992
Design control in a high level synthesis system.
Microprocess. Microprogramming, 1992

Heuristics for branch-and-bound global allocation.
Proceedings of the conference on European design automation, 1992

1991
A hardware allocator guided by cost functions.
Microprocessing and Microprogramming, 1991

1982
Multimicrocomputer system for building with full service facility automation.
Proceedings of the 5th ACM SIGSMALL symposium on Small systems, 1982

1977
A Multilingual High Level Processor.
Proceedings of the Information Processing, 1977

High level languages processor architecture.
Proceedings of the 1977 annual conference, 1977


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