Francisco Rangel-Patino
Orcid: 0000-0001-9633-2533
According to our database1,
Francisco Rangel-Patino
authored at least 7 papers
between 2014 and 2020.
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Bibliography
2020
A Holistic Formulation for System Margining and Jitter Tolerance Optimization in Industrial Post-Silicon Validation.
IEEE Trans. Emerg. Top. Comput., 2020
Machine Learning Techniques and Space Mapping Approaches to Enhance Signal and Power Integrity in High-Speed Links and Power Delivery Networks.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
2018
Direct optimization of a PCI express link equalization in industrial post-silicon validation.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Transmitter and Receiver Equalizers Optimization Methodologies for High-Speed Links in Industrial Computer Platforms Post-Silicon Validation.
Proceedings of the IEEE International Test Conference, 2018
2014
Backplane/FDA correlation-FDA replacing commercial backplanes for SoC ethernet electrical validation.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014