Francisco José Ballester-Merelo

According to our database, Francisco José Ballester-Merelo authored at least 11 papers between 2000 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Design, Implementation, and Configuration of Laser Systems for Vehicle Detection and Classification in Real Time.

Nieves Gallego Ripoll, Luís Enrique Gómez Aguilera, Ferran Mocholí Belenguer, Antonio Mocholí Salcedo, Francisco José Ballester-Merelo

Sensors, 2021

The Event Detection System in the NEXT-White Detector.

Raúl Esteve Bosch, José F. Toledo Alarcón, Vicente Herrero-Bosch, Ander Simón Estévez, Francesc Monrabal Capilla, Vicente Álvarez Puerta, Javier Rodríguez Samaniego, Marc Querol Segura, Francisco José Ballester-Merelo

Sensors, 2021

2018

Real-Time Early Warning System Design for Pluvial Flash Floods - A Review.

Melisa Acosta-Coll, Francisco José Ballester-Merelo, Marcos Martínez-Peiró, Emiro De la Hoz-Franco

Sensors, 2018

2008

Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management.

Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve

Microprocess. Microsystems, 2008

2004

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices.

Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró

Microprocess. Microsystems, 2004

2D-DCT on FPGA by polynomial transformation in two-dimensions.

Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Architectures for ICT on FPGA.

Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

FPGA Custom DSP for ECG Signal Analysis and Compression.

Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer

Proceedings of the Field Programmable Logic and Application, 2004

2003

A new inverse discrete wavelet packet transform architecture.

Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá

Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003

Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA.

Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2000

Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation.

Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo

Proceedings of the 13th International Symposium on System Synthesis, 2000