Francisco Gilabert Villamón
According to our database1,
Francisco Gilabert Villamón
authored at least 14 papers
between 2006 and 2015.
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Bibliography
2015
J. Supercomput., 2015
2013
ACM Trans. Embed. Comput. Syst., 2013
2010
Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip.
Proceedings of the NOCS 2010, 2010
Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoC.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
Proceedings of the Design, Automation and Test in Europe, 2009
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
Proceedings of the 2009 International Conference on Complex, 2009
Proceedings of the Embedded Systems Design and Verification, 2009
2008
IEEE Comput. Archit. Lett., 2008
EST2uni: an open, parallel tool for automated EST analysis and database creation, with a data mining web interface and microarray expression data integration.
BMC Bioinform., 2008
Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Proceedings of the 14th International Conference on Parallel and Distributed Systems, 2008
2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
2006
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006