Francisco Garcia-Herrero
Orcid: 0000-0001-6719-9681Affiliations:
- Complutense University of Madrid, Spain
According to our database1,
Francisco Garcia-Herrero
authored at least 45 papers
between 2011 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
Protecting the CCSDS 123.0-B-2 Compression Algorithm Against Single-Event Upsets for Space Applications.
IEEE Trans. Computers, March, 2025
2024
Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024
Noise-Aware Compilation Techniques for Enhanced Fault-Tolerant Preparation of Polar Code States.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
On the Use of Calibration Data in Error-Aware Compilation Techniques for NISQ Devices.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
Proceedings of the IEEE International Conference on Communications, 2024
2023
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension.
IEEE Trans. Aerosp. Electron. Syst., October, 2023
RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography.
IEEE Trans. Computers, March, 2023
Proceedings of the 12th International Symposium on Topics in Coding, 2023
2022
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates.
J. Supercomput., 2022
Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors.
Comput. Electr. Eng., 2022
2021
IEEE Trans. Emerg. Top. Comput., 2021
Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
Sensors, 2021
Integr., 2021
Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes.
IEEE Access, 2021
Project-Based Learning with historic buildings: immersion in real training environments for the Degree in Technical Architecture.
Proceedings of the International Conference of Innovation, 2021
2020
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase.
IEEE Trans. Circuits Syst., 2020
Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA.
Circuits Syst. Signal Process., 2020
Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications.
IEEE Access, 2020
2019
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems.
Circuits Syst. Signal Process., 2019
Circuits Syst. Signal Process., 2019
2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2016
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Commun. Lett., 2014
Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree.
IEEE Commun. Lett., 2014
Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014
2013
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes.
Circuits Syst. Signal Process., 2013
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Commun. Lett., 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Circuits Syst. Signal Process., 2011