Francisco Eugenio Potestad-Ordóñez
Orcid: 0000-0003-4107-2396
According to our database1,
Francisco Eugenio Potestad-Ordóñez
authored at least 12 papers
between 2016 and 2024.
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Bibliography
2024
Sensors, March, 2024
Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024
2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022
2021
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors, 2021
IEEE Access, 2021
2020
Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.
Sensors, 2020
Rev. Iberoam. de Tecnol. del Aprendiz., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2018
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016