Francisco Eugenio Potestad-Ordóñez

Orcid: 0000-0003-4107-2396

According to our database1, Francisco Eugenio Potestad-Ordóñez authored at least 12 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
Protecting FPGA-Based Cryptohardware Implementations from Fault Attacks Using ADCs.
Sensors, March, 2024

Design and Evaluation of Combined Hardware FIA and SCA Countermeasures for AES Cipher.
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024


2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022

2021
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.
IEEE Access, 2021

2020
Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.
Sensors, 2020

An Academic Approach to FPGA Design Based on a Distance Meter Circuit.
Rev. Iberoam. de Tecnol. del Aprendiz., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Vulnerability Analysis of Trivium FPGA Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2016
Fault attack on FPGA implementations of Trivium stream cipher.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016


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