Francesco Stefanni
Orcid: 0000-0002-5706-4799
According to our database1,
Francesco Stefanni
authored at least 33 papers
between 2008 and 2018.
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Bibliography
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2017
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017
Proceedings of the 2017 Forum on Specification and Design Languages, 2017
2016
Proceedings of the 2016 Forum on Specification and Design Languages, 2016
2015
J. Electron. Test., 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
UNIVERCM: The UNIversal VERsatile Computational Model for Heterogeneous System Integration.
IEEE Trans. Computers, 2013
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Code generation alternatives to reduce heterogeneous embedded systems to homogeneity.
Proceedings of the 2013 Forum on specification and Design Languages, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
2012
HDTLib: an efficient implementation of SystemC data types for fast simulation at different abstraction levels.
Des. Autom. Embed. Syst., 2012
Proceedings of the 7th IEEE International Symposium on Industrial Embedded Systems, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
PhD thesis, 2011
Communication-aware middleware-based design-space exploration for Networked Embedded Systems.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011
Proceedings of the 2011 Forum on Specification & Design Languages, 2011
2010
EURASIP J. Embed. Syst., 2010
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Modeling of Communication Infrastructure for Design-Space Exploration.
Proceedings of the 2010 Forum on specification & Design Languages, 2010
2009
Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the Languages for Embedded Systems and their Applications, 2008
Proceedings of the Forum on specification and Design Languages, 2008
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008