Francesco Restuccia

Orcid: 0000-0001-6955-1888

Affiliations:

University of California at San Diego, San Diego, CA, USA

According to our database¹, Francesco Restuccia authored at least 25 papers between 2019 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2024

TOP: Towards Open & Predictable Heterogeneous SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, December, 2024

CGRA4ML: A Framework to Implement Modern Neural Networks for Scientific Edge Computing.

[BibT_eX]

[DOI]

CoRR, 2024

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Isadora: automated information-flow property generation for hardware security verification.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., November, 2023

A Framework for Design, Verification, and Management of SoC Access Control Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, February, 2023

Bounding Memory Access Times in Multi-Accelerator Architectures on FPGA SoCs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2023

Security Verification of the OpenTitan Hardware Root of Trust.

[BibT_eX]

[DOI]

IEEE Secur. Priv., 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.

[BibT_eX]

[DOI]

Jasper Van Woudenberg

Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022

Cut and Forward: Safe and Secure Communication for FPGA System on Chips.

[BibT_eX]

[DOI]

Francesco Restuccia

Ryan Kastner

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ARTe: Providing real-time multitasking to Arduino.

[BibT_eX]

[DOI]

J. Syst. Softw., 2022

Toward Hardware Security Property Generation at Scale.

[BibT_eX]

[DOI]

IEEE Secur. Priv., 2022

A Remote Control System for Emergency Ventilators During SARS-CoV-2.

[BibT_eX]

[DOI]

Michael Barrow

Francesco Restuccia

Mustafa S. Gobulukoglu

Enrico Rossi

Ryan Kastner

IEEE Embed. Syst. Lett., 2022

PAC-PL: Enabling Control-Flow Integrity with Pointer Authentication in FPGA SoC Platforms.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Real-Time and Embedded Technology and Applications Symposium, 2022

Hardware Acceleration of Deep Neural Networks for Autonomous Driving on FPGA-based SoC.

[BibT_eX]

[DOI]

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

Automating hardware security property generation: invited.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

AKER: A Design and Verification Framework for Safe andSecure SoC Access Control.

[BibT_eX]

[DOI]

Francesco Restuccia

Andres Meza

Ryan Kastner

CoRR, 2021

A Methodology For Creating Information Flow Specifications of Hardware Designs.

[BibT_eX]

[DOI]

CoRR, 2021

Time-Predictable Acceleration of Deep Neural Networks on FPGA SoC Platforms.

[BibT_eX]

[DOI]

Francesco Restuccia

Alessandro Biondi

Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Aker: A Design and Verification Framework for Safe and Secure SoC Access Control.

[BibT_eX]

[DOI]

Francesco Restuccia

Andres Meza

Ryan Kastner

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Isadora: Automated Information Flow Property Generation for Hardware Designs.

[BibT_eX]

[DOI]

Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021

2020

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs (Artifact).

[BibT_eX]

[DOI]

Dagstuhl Artifacts Ser., 2020

Safely Preventing Unbounded Delays During Bus Transactions in FPGA-based SoC.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Modeling and Analysis of Bus Contention for Hardware Accelerators in FPGA SoCs.

[BibT_eX]

[DOI]

Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

AXI HyperConnect: A Predictable, Hypervisor-level Interconnect for Hardware Accelerators in FPGA SoC.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Is Your Bus Arbiter Really Fair? Restoring Fairness in AXI Interconnects for FPGA SoCs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Francesco Restuccia

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