Francesco Pessolano

According to our database1, Francesco Pessolano authored at least 12 papers between 1999 and 2006.

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Bibliography

2006
The Holy Grail of Holistic Low-Power Design.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

2005
Glitch-free discretely programmable clock generation on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Limits to performance spread tuning using adaptive voltage and body biasing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

How to determine the necessity for emerging solutions.
Proceedings of the 42nd Design Automation Conference, 2005

2004
A 260ps Quasi-static ALU in 90nm CMOS.
Proceedings of the Integrated Circuit and System Design, 2004

Technology exploration for adaptive power and frequency scaling in 90nm CMOS.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

On ambient intelligence, needful things and process technologies.
Proceedings of the 33rd European Solid-State Circuits Conference, 2004

2003
Analysis of High-Speed Logic Families.
Proceedings of the Integrated Circuit and System Design, 2003

2002
MDSP: A High-Performance Low-Power DSP Architecture.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2000
Asynchronous First-in First-out Queues.
Proceedings of the Integrated Circuit Design, 2000

An Objective Measure of Digital System Design Quality.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

1999
Heterogeneous Clustered Processors: Organisation and Design.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999


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