Francesco Beneventi
Orcid: 0009-0009-5454-4197
According to our database1,
Francesco Beneventi
authored at least 38 papers
between 2011 and 2024.
Collaborative distances:
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Bibliography
2024
Future Gener. Comput. Syst., 2024
2023
Design of an energy aware petaflops class high performance cluster based on power architecture.
CoRR, 2023
Experimenting with Emerging ARM and RISC-V Systems for Decentralised Machine Learning.
CoRR, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
Monte Cimone: Paving the Road for the First Generation of RISC-V High-Performance Computers.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022
2021
Proceedings of the High Performance Computing - ISC High Performance Digital 2021 International Workshops, Frankfurt am Main, Germany, June 24, 2021
Prediction of Thermal Hazards in a Real Datacenter Room Using Temporal Convolutional Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2019
Proceedings of the 48th International Conference on Parallel Processing, 2019
2018
IEEE Des. Test, 2018
A Scalable Framework for Online Power Modelling of High-Performance Computing Nodes in Production.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018
The D.A.V.I.D.E. big-data-powered fine-grain power and performance monitoring support.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
Design of an Energy Aware Petaflops Class High Performance Cluster Based on Power Architecture.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017
Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Proceedings of the International Conference on High Performance Computing & Simulation, 2016
Proceedings of the IECON 2016, 2016
2014
Bias-Compensated Least Squares Identification of Distributed Thermal Models for Many-Core Systems-on-Chip.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Computers, 2014
Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the 3rd Many-core Applications Research Community (MARC) Symposium. Proceedings of the 3rd MARC Symposium, 2011
Proceedings of 20th International Conference on Computer Communications and Networks, 2011