Francesc Fons

Orcid: 0000-0001-5901-7534

According to our database1, Francesc Fons authored at least 34 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2024
Vehicular network processor design for scalability & automation: Elastic Gateway SoC concept & builder.
J. Syst. Archit., January, 2024

Elastic Gateway SoC design: A HW-centric architecture for inline In-Vehicle Network processing.
Veh. Commun., 2024

2023
Elastic gateway SoC proof of concept: Experiments design and performance evaluation.
Veh. Commun., October, 2023

2022
EnGINE: Flexible Research Infrastructure for Reliable and Scalable Time Sensitive Networks.
J. Netw. Syst. Manag., 2022

Hardware Acceleration of Data Distribution Service (DDS) for Automotive Communication and Computing.
IEEE Access, 2022

The Future Roadmap of In-Vehicle Network Processing: A HW-Centric (R-)evolution.
IEEE Access, 2022

Elastic Gateway Functional Safety Architecture and Deployment: A Case Study.
IEEE Access, 2022

Methodology and Infrastructure for TSN-Based Reproducible Network Experiments.
IEEE Access, 2022

SmartNIC-based Load Management and Network Health Monitoring for Time Sensitive Applications.
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022

Build Automation Framework for Design Validation of Automotive Gateway Controllers.
Proceedings of the IFIP Networking Conference, 2022

2021
Elastic Queueing Engine for Time Sensitive Networking.
Proceedings of the 93rd IEEE Vehicular Technology Conference, 2021

Traffic Shaping Engine for Time Sensitive Networking Integration within In-Vehicle Networks.
Proceedings of the 13th IEEE Vehicular Networking Conference, 2021

Demo: Environment for Generic In-vehicular Network Experiments - EnGINE.
Proceedings of the 13th IEEE Vehicular Networking Conference, 2021

Loopback Strategy for TSN-compliant Traffic Queueing and Shaping in Automotive Gateways.
Proceedings of the 2021 IEEE Conference on Network Function Virtualization and Software Defined Networks, 2021

Loopback strategy for in-vehicle network processing in automotive gateway network on chip.
Proceedings of the NoCArc '21: Proceedings of the 14th International Workshop on Network on Chip Architectures, Virtual Event, Greece, October 18, 2021

Precise real-time monitoring of time-critical flows.
Proceedings of the CoNEXT '21: The 17th International Conference on emerging Networking EXperiments and Technologies, Virtual Event, Munich, Germany, December 7, 2021

EnGINE: Developing a Flexible Research Infrastructure for Reliable and Scalable Intra-Vehicular TSN Networks.
Proceedings of the 17th International Conference on Network and Service Management, 2021

PDU Normalizer Engine for Heterogeneous In-Vehicle Networks in Automotive Gateways.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

Enhancements for Hardware-based IEEE802.1CB embedded in Automotive Gateway System-on-Chip.
Proceedings of the ANCS '21: Symposium on Architectures for Networking and Communications Systems, Layfette, IN, USA, December 13, 2021

2013
Fast Self-Reconfigurable Embedded System on Spartan-3.
J. Univers. Comput. Sci., 2013

Real-time embedded systems powered by FPGA dynamic partial self-reconfiguration: a case study oriented to biometric recognition applications.
J. Real Time Image Process., 2013

2012
Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications.
J. Signal Process. Syst., 2012

FPGA-based Personal Authentication Using Fingerprints.
J. Signal Process. Syst., 2012

Biometrics-based consumer applications driven by reconfigurable hardware architectures.
Future Gener. Comput. Syst., 2012

2011
Run-time self-reconfigurable 2D convolver for adaptive image processing.
Microelectron. J., 2011

2010
Fingerprint Image Processing Acceleration Through Run-Time Reconfigurable Hardware.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2008
Self-recofigurable embedded systems on Spartan-3.
Proceedings of the FPL 2008, 2008

2007
Design of a hardware accelerator for fingerprint alignment.
Proceedings of the FPL 2007, 2007

2006
System-on-Chip Design of a Fuzzy Logic Controller Based on Dynamically Reconfigurable Hardware.
Int. Trans. Syst. Sci. Appl., 2006

Hardware-Software Co-design of a Dynamically Reconfigurable FPGA-based Fuzzy Logic Controller.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Custom-Made Design of a Digital PID Control System.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

Dynamically Reconfigurable CORDIC Coprocessor for Trigonometric.
Proceedings of the ARCS 2006, 2006

Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2004
FPGA Implementation of the Ridge Line Following Fingerprint Algorithm.
Proceedings of the Field Programmable Logic and Application, 2004


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