Florian Huemer

Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024

2023

ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on Asynchronous Circuits and Systems, 2023

2022

On SAT-Based Model Checking of Speed-Independent Circuits.

[BibT_eX]

[DOI]

Robert Najvirt

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

2021

An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020

Timing Domain Crossing using Muller Pipelines.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on Asynchronous Circuits and Systems, 2020

2019

An Experimental Study of Metastability-Induced Glitching Behavior.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

2018

Refined metastability characterization using a time-to-digital converter.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Partially Systematic Constant-Weight Codes for Delay-Insensitive Communication.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Asynchronous Circuits and Systems, 2018

2017

Measuring metastability using a time-to-digital converter.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016

Fault-Tolerant Clock Synchronization with High Precision.

[BibT_eX]

[DOI]

Attila Kinali

Christoph Lenzen

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

A new coding scheme for fault tolerant 4-phase delay-insensitive codes.

[BibT_eX]

[DOI]

Jakob Lechner

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015

Methods for analysing and improving the fault resilience of delay-insensitive codes.

[BibT_eX]

[DOI]

Jakob Lechner