Florent Flament

According to our database1, Florent Flament authored at least 14 papers between 2007 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography.
Int. J. Reconfigurable Comput., 2012

2011
Enhancement of simple electro-magnetic attacks by pre-characterization in frequency domain and demodulation techniques.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.
IEEE Trans. Computers, 2010

Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics.
Int. J. Reconfigurable Comput., 2010

Cross-Correlation Cartography.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Evaluation of White-Box and Grey-Box Noekeon Implementations in FPGA.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

First Principal Components Analysis: A New Side Channel Distinguisher.
Proceedings of the Information Security and Cryptology - ICISC 2010, 2010

Entropy-based Power Attack.
Proceedings of the HOST 2010, 2010

Characterization of the Electromagnetic Side Channel in Frequency Domain.
Proceedings of the Information Security and Cryptology - 6th International Conference, 2010

Countering early evaluation: an approach towards robust dual-rail precharge logic.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

2009
DPL on Stratix II FPGA: What to Expect?.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
An 8x8 run-time reconfigurable FPGA embedded in a SoC.
Proceedings of the 45th Design Automation Conference, 2008

2007
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.
IEEE Des. Test Comput., 2007


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