Flavio Ponzina

According to our database, Flavio Ponzina authored at least 15 papers between 2020 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

An Energy Efficient Soft SIMD Microarchitecture and Its Application on Quantized CNNs.

Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Mohit Gupta, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor

IEEE Trans. Very Large Scale Integr. Syst., June, 2024

E-QUARTIC: Energy Efficient Edge Ensemble of Convolutional Neural Networks for Resource-Optimized Learning.

Le Zhang, Onat Güngör, Flavio Ponzina, Tajana Rosing

CoRR, 2024

MicroHD: An Accuracy-Driven Optimization of Hyperdimensional Computing Algorithms for TinyML systems.

Flavio Ponzina, Tajana Rosing

CoRR, 2024

LionHeart: A Layer-based Mapping Framework for Heterogeneous Systems with Analog In-Memory Computing Tiles.

Corey Lammie, Flavio Ponzina, Yuxuan Wang, Joshua Klein, Marina Zapater, Irem Boybat, Abu Sebastian, Giovanni Ansaloni, David Atienza

CoRR, 2024

DBFS: Dynamic Bitwidth-Frequency Scaling for Efficient Software-defined SIMD.

Pengbo Yu, Flavio Ponzina, Alexandre Levisse, Dwaipayan Biswas, Giovanni Ansaloni, David Atienza, Francky Catthoor

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

2023

Overflow-free Compute Memories for Edge AI Acceleration.

Flavio Ponzina, Marco Rios, Alexandre Levisse, Giovanni Ansaloni, David Atienza

ACM Trans. Embed. Comput. Syst., October, 2023

An Error-Based Approximation Sensing Circuit for Event-Triggered Low-Power Wearable Sensors.

Silvio Zanoli, Flavio Ponzina, Tomás Teijeiro, Alexandre Levisse, David Atienza

IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2023

Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference.

Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza

IEEE Trans. Emerg. Top. Comput., 2023

2022

A Hardware/Software Co-Design Vision for Deep Learning at the Edge.

Flavio Ponzina, Simone Machetti, Marco Rios, Benoît Walter Denkinger, Alexandre Levisse, Giovanni Ansaloni, Miguel Peón Quirós, David Atienza

IEEE Micro, 2022

Error Resilient In-Memory Computing Architecture for CNN Inference on the Edge.

Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

An Accuracy-Driven Compression Methodology to Derive Efficient Codebook-Based CNNs.

Flavio Ponzina, Miguel Peón Quirós, Giovanni Ansaloni, David Atienza

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022

2021

E²CNNs: Ensembles of Convolutional Neural Networks to Improve Robustness Against Memory Errors in Edge-Computing Devices.

Flavio Ponzina, Miguel Peón Quirós, Andreas Burg, David Atienza

IEEE Trans. Computers, 2021

A Flexible In-Memory Computing Architecture for Heterogeneously Quantized CNNs.

Flavio Ponzina, Marco Rios, Giovanni Ansaloni, Alexandre Levisse, David Atienza

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Running Efficiently CNNs on the Edge Thanks to Hybrid SRAM-RRAM In-Memory Computing.

Marco Rios, Flavio Ponzina, Giovanni Ansaloni, Alexandre Levisse, David Atienza

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Impact of Memory Voltage Scaling on Accuracy and Resilience of Deep Learning Based Edge Devices.

Benoît W. Denkinger, Flavio Ponzina, Soumya Basu, Andrea Bonetti, Szabolcs Balási, Martino Ruggiero, Miguel Peón Quirós, Davide Rossi, Andreas Burg, David Atienza

IEEE Des. Test, 2020