Filippo Carloni

Orcid: 0000-0001-7084-7184

According to our database1, Filippo Carloni authored at least 13 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
POCA: A PYNQ Offloaded Cryptographic Accelerator on Embedded FPGA-Based Systems.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

ALVEARE: a Domain-Specific Framework for Regular Expressions.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

One Automaton to Rule Them All: Beyond Multiple Regular Expressions Execution.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2024

2023
An Energy-Efficient Domain-Specific Architecture for Regular Expressions.
IEEE Trans. Emerg. Top. Comput., 2023

On the Genome Sequence Alignment FPGA Acceleration via KSW2z.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

YARB: a Methodology to Characterize Regular Expression Matching on Heterogeneous Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Enabling Efficient Regular Expression Matching at the Edge through Domain-Specific Architectures.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

Improving Sleep Quality Through an Arduino-Based Environment Sleep Monitoring System.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

Co-designing an FPGA-Accelerated Encryption Library With PYNQ: The Pynqrypt Case Study.
Proceedings of the 20th IEEE International Conference on Smart Technologies, 2023

2022
BrainTrack: A Replicable and Accessible Methodology for Customized Brain-Machine Interface Applications.
Proceedings of the 7th IEEE Forum on Research and Technologies for Society and Industry Innovation, 2022

ROH-BOT: An IoT Wearable and Inclusive Health Device for Remote Patient Monitoring With Different Alarm Systems.
Proceedings of the 7th IEEE Forum on Research and Technologies for Society and Industry Innovation, 2022

2020
Enabling transparent hardware acceleration on Zynq SoC for scientific computing.
SIGBED Rev., 2020

2019
Speeding Up Resting State Networks Recognition via a Hardware Accelerator.
Proceedings of the 2019 IEEE EMBS International Conference on Biomedical & Health Informatics, 2019


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