Ferruccio Barsi

Vlady Ravelomanana

IEEE Trans. Mob. Comput., 2011

2009

Asynchronous Corona Training Protocols in Wireless Sensor and Actor Networks.

[BibT_eX]

[DOI]

Alan A. Bertossi

Francesco Betti Sorbelli

Roberto Ciotti

Stephan Olariu

IEEE Trans. Parallel Distributed Syst., 2009

Error control by product codes in arithmetic units.

[BibT_eX]

[DOI]

Int. J. Parallel Emergent Distributed Syst., 2009

Cheapest Paths in Multi-interface Networks.

[BibT_eX]

[DOI]

Alfredo Navarra

Proceedings of the Distributed Computing and Networking, 10th International Conference, 2009

2008

Efficient heuristics for data broadcasting on multiple channels.

[BibT_eX]

[DOI]

Wirel. Networks, 2008

Efficient binary schemes for training heterogeneous sensor and actor networks.

[BibT_eX]

[DOI]

Alfredo Navarra

Proceedings of the 1st ACM International Workshop on Heterogeneous Sensor and Actor Networks, 2008

2007

Asynchronous training in SANET.

[BibT_eX]

[DOI]

Francesco Betti Sorbelli

Roberto Ciotti

Alan A. Bertossi

Stephan Olariu

Proceedings of the First ACM Workshop on Sensor and Actor Networks, 2007

Asynchronous Training in Wireless Sensor Networks.

[BibT_eX]

[DOI]

Alan A. Bertossi

Francesco Betti Sorbelli

Roberto Ciotti

Stephan Olariu

Proceedings of the Algorithmic Aspects of Wireless Sensor Networks, 2007

1995

Fast base extension and precise scaling in RNS for look-up table implementations.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 1995

Addendum to "A Fully Parallel Algorithm for Residue to Binary Conversion".

[BibT_eX]

[DOI]

Inf. Process. Lett., 1995

A Fully Parallel Algorithm for Residue to Binary Conversion.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1995

Decoding Residue Codes.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1995

1994

Time Optimal Mixed Radix Conversion for Residue Number Applications.

[BibT_eX]

[DOI]

Comput. J., 1994

1992

Adding Flexibility to Hybrid Number Systems.

[BibT_eX]

[DOI]

Comput. J., 1992

1991

Mod m Arithmetic in Binary Systems.

[BibT_eX]

[DOI]

Inf. Process. Lett., 1991

A VLSI architecture for RNS with MI adders.

[BibT_eX]

[DOI]

Enrico Martinelli

Integr., 1991

1985

Table Look-up Graphic Interpolation.

[BibT_eX]

[DOI]

Proceedings of the 6th European Computer Graphics Conference and Exhibition, 1985

1984

A Fast VLSI Conversion Between Binary and Residue Systems.

[BibT_eX]

[DOI]

Giuseppe Alia

Enrico Martinelli

Inf. Process. Lett., 1984

A fast near optimum VLSI implementation of FFT using residue number systems.

[BibT_eX]

[DOI]

Giuseppe Alia

Enrico Martinelli

Integr., 1984

1980

Error Codes Constructed in Residue Number Systems with Non-Pairwise-Prime Moduli

[BibT_eX]

[DOI]

Inf. Control., July, 1980

1978

A Class of Multiple-Error-Correcting Arithmetic Residue Codes

[BibT_eX]

[DOI]

Inf. Control., January, 1978

Improved decoding algorithms for arithmetic residue codes (Corresp.).

[BibT_eX]

[DOI]

IEEE Trans. Inf. Theory, 1978

Arithmetic Codes in Residue Number Systems with Magnitude Index.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1978

1976

A Theory of Diagnosability of Digital Systems.

[BibT_eX]

[DOI]

Fabrizio Grandoni

IEEE Trans. Computers, 1976

1974

Error Detection and Correction by Product Codes in Residue Number Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1974

1973

Error Correcting Properties of Redundant Residue Number Systems.

[BibT_eX]

[DOI]