Fernando García-Redondo

Orcid: 0000-0001-7090-8821

Affiliations:
  • Arm Ltd.


According to our database1, Fernando García-Redondo authored at least 22 papers between 2015 and 2024.

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Bibliography

2024
A DTCO Framework for 3D NAND Flash Readout.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
AR-PIM: An Adaptive-Range Processing-in-Memory Architecture.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes.
Proceedings of the 53rd IEEE European Solid-State Device Research Conference, 2023

2022
ML-HW Co-Design of Noise-Robust TinyML Models and Always-On Analog Compute-in-Memory Edge Accelerator.
IEEE Micro, 2022

SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

SACA: System-level Analog CIM Accelerators Simulation Framework: Accurate Simulation of Non-Ideal Components.
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2021
AnalogNets: ML-HW Co-Design of Noise-robust TinyML Models and Always-On Analog Compute-in-Memory Accelerator.
CoRR, 2021

A Compact Model for Scalable MTJ Simulation.
CoRR, 2021

A Fokker-Planck Solver to Model MTJ Stochasticity.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

-17 dBm Differential charge pump EPC Gen2 UHF RFID demodulator for 9 dB receive sensitivity boost.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
27.2 M0N0: A Performance-Regulated 0.8-to-38MHz DVFS ARM Cortex-M33 SIMD MCU with 10nW Sleep Power.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Training DNN IoT Applications for Deployment On Analog NVM Crossbars.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

2019
Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Time-Domain Current-Mode MAC Engine for Analogue Neural Networks in Flexible Electronics.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017
Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Advanced integration of variability and degradation in RRAM SPICE compact models.
Proceedings of the 14th International Conference on Synthesis, 2017

2016
SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Reliable design methodology: The combined effect of radiation, variability and temperature.
Proceedings of the 13th International Conference on Synthesis, 2016

2015
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A thermal adaptive scheme for reliable write operation on RRAM based architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015


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