Fernanda D. V. R. Oliveira

Orcid: 0000-0002-1012-6673

According to our database1, Fernanda D. V. R. Oliveira authored at least 22 papers between 2012 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Tracking Analysis of the ℓ <sub>0</sub>-LMS Algorithm.
Circuits Syst. Signal Process., December, 2024

Analyzing the LMS Weight Error Covariance Matrix: An Exact Expectation Approach.
Circuits Syst. Signal Process., July, 2024

Hardware designs for convolutional neural networks: Memoryful, memoryless and cached.
Integr., January, 2024

Layout Design of an Asynchronous Time-Based Image Sensor with Shared DVS Module.
Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

MOSFET-C Filter Design using Genetic Algorithm with Restricted Mutation for Gate Multiplicity.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
Redes Neurais Profundas com Saídas Antecipadas para Imagens com Distorção em Ambientes de Nuvem.
Proceedings of the 41st Brazilian Symposium on Computer Networks and Distributed Systems, 2023

2022
Neuromorphic Hardware Applied in the Development of Low-Power IoTs.
Proceedings of the Symposium on Internet of Things, 2022

2021
Non-Memoryless vs. Memoryless Hardware Architectures for Convolutional Neural Networks.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

Early-exit deep neural networks for distorted images: providing an efficient edge offloading.
Proceedings of the IEEE Global Communications Conference, 2021

2020
An Exact Expectation Model for the LMS Tracking Abilities.
IEEE Trans. Signal Process., 2020

Comparison between Digital Tone-Mapping Operators and a Focal-Plane Pixel-Parallel Circuit.
Signal Process. Image Commun., 2020

Event-Based CMOS Image Sensor with Shared DVS Module for Pixel Area Reduction.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2018
Color Tone-Mapping Circuit for a Focal-Plane Implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Gaussian Pyramid: Comparative Analysis of Hardware Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
High-level Performance Evaluation of Object Detection based on Massively Parallel Focal-plane Acceleration Requiring Minimum Pixel Area Overhead.
Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2016), 2016

Focal-plane image encoder with cascode current mirrors and increased vector quantization bit rate.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Image Sensing Scheme Enabling Fully-Programmable Light Adaptation and Tone Mapping with a Single Exposure: Demo.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Focal-Plane Scale Space Generation with a 6T Pixel Architecture.
Proceedings of the Image Sensors and Imaging Systems 2016, 2016

2015
Influence of cascode and simple current mirrors in inner product implementations for CMOS imagers.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

CMOS image sensor architecture for focal plane early vision processing.
Proceedings of the 9th International Conference on Distributed Smart Camera, 2015

2013
CMOS Imager With Focal-Plane Analog Image Compression Combining DPCM and VQ.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Current-mode analog integrated circuit for focal-plane image compression.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012


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