Fengwei An
Orcid: 0000-0002-7554-7938
According to our database1,
Fengwei An
authored at least 64 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2024
IEEE Trans. Instrum. Meas., 2024
Proceedings of the Medical Image Computing and Computer Assisted Intervention - MICCAI 2024, 2024
Live Demonstration: A Video Denoising Co-processor with Non-local Means Algorithm for FHD 30fps Image Sensor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Live Demonstration: A 1920×1080 129fps 4.3pJ/pixel Stereo-Matching Processor for Low-power Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
BESA: Pruning Large Language Models with Blockwise Parameter-Efficient Sparsity Allocation.
Proceedings of the Twelfth International Conference on Learning Representations, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
2023
Anti-Aliasing and Anti-Color-Artifact Demosaicing for High-Resolution CMOS Image Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2023
An 11.6aF/kPa Mechanical Stress Sensor With 0.808% Temperature-Drift Oscillator for Flip-Chip Packaging.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
A Reconfigurable Coprocessor for Simultaneous Localization and Mapping Algorithms in FPGA.
IEEE Trans. Circuits Syst. II Express Briefs, 2023
An Energy-Efficient, Resource-Efficient and High Frame-Rate End-to-End Pedestrian Detector Using HOG-SVM for Intelligent Edge Devices.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
A Non-Local Means Denoising Co-Processor with Data Reuse Scheme and Dual-Clock Domain for High Resolution Image Sensor.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 15th IEEE International Conference on ASIC, 2023
Live Demonstration: Supervised-learning-based Visual Quantification for Image Enhancement.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023
2022
Asynchronous Double-Frame-Exposure Binocular-Camera With Pixel-Level Pipeline Architecture for High-Speed Motion Tracking.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Compact Hardware Architecture for Bilateral Filter With the Combination of Approximate Computing and Look-Up Table.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 4.29nJ/pixel Stereo Depth Coprocessor With Pixel Level Pipeline and Region Optimized Semi-Global Matching for IoT Application.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A Reconfigurable Visual-Inertial Odometry Accelerated Core with High Area and Energy Efficiency for Autonomous Mobile Robots.
Sensors, 2022
Five-Direction Occlusion Filling with Five Layer Parallel Two-Stage Pipeline for Stereo Matching with Sub-Pixel Disparity Map Estimation.
Sensors, 2022
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection.
IEEE Des. Test, 2022
Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
A 14.39ppm/kPa Stress Sensor with Low Temperature-drift and High Linearity for turbulence Stress.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022
2021
Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching Algorithm.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021
Proceedings of the IEEE International Conference on Real-time Computing and Robotics, 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Pseudo 943 million Frames Per Rate High-Speed Camera with Asynchronous Double-Frame Exposure for Motion Estimation.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Reconfigurable Matrix Multiplication Coprocessor with High Area and Energy Efficiency for Visual Intelligent and Autonomous Mobile Robots.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
FPGA-Based Low-Visibility Enhancement Accelerator for Video Sequence by Adaptive Histogram Equalization With Dynamic Clip-Threshold.
IEEE Trans. Circuits Syst., 2020
A Multi-Class Objects Detection Coprocessor With Dual Feature Space and Weighted Softmax.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A Multi-Core Object Detection Coprocessor for Multi-Scale/Type Classification Applicable to IoT Devices.
Sensors, 2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm.
IEICE Trans. Inf. Syst., 2019
A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier.
IEEE Access, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition.
Proceedings of the International Conference on Field-Programmable Technology, 2019
2018
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space.
IEEE Trans. Circuits Syst. Video Technol., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
2017
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures.
Sensors, 2017
A Vector-Quantization Compression Circuit With On-Chip Learning Ability for High-Speed Image Sensor.
IEEE Access, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
IEEE Trans. Multi Scale Comput. Syst., 2016
k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching.
IEICE Trans. Electron., 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
Adv. Robotics, 2014
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2014
A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
LVQ neural network SoC adaptable to different on-chip learning and recognition applications.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design.
J. Syst. Archit., 2013
2012
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching.
IEICE Trans. Inf. Syst., 2012
Human recognition with a hardware-accelerated multi-prototype learning and classification system.
Proceedings of the 2012 IEEE International Conference on Robotics and Biomimetics, 2012
Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012
2011
Proceedings of the 2011 IEEE International Conference on Robotics and Biomimetics, 2011