Feng Shi

Orcid: 0000-0001-5175-9760

Affiliations:
  • Beijing Institute of Technology, School of Computer Science and Technology, China (PhD 1999)


According to our database1, Feng Shi authored at least 39 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Revisiting thread configuration of SpMV kernels on GPU: A machine learning based approach.
J. Parallel Distributed Comput., March, 2024

2022
TaiChi: A Hybrid Compression Format for Binary Sparse Matrix-Vector Multiplication on GPU.
IEEE Trans. Parallel Distributed Syst., 2022

2021
AMF-CSR: Adaptive Multi-Row Folding of CSR for SpMV on GPU.
Proceedings of the 27th IEEE International Conference on Parallel and Distributed Systems, 2021

2020
Attentive boundary aware network for multi-scale skin lesion segmentation with adversarial training.
Multim. Tools Appl., 2020

Sparse matrix partitioning for optimizing SpMV on CPU-GPU heterogeneous platforms.
Int. J. High Perform. Comput. Appl., 2020

MMSparse: 2D partitioning of sparse matrix based on mathematical morphology.
Future Gener. Comput. Syst., 2020

Fast Piecewise Polynomial Fitting of Time-Series Data for Streaming Computing.
IEEE Access, 2020

2019
Ontology-based code snippets management in a cloud environment.
J. Ambient Intell. Humaniz. Comput., 2019

KernelGraph: Understanding the kernel in a graph.
Inf. Vis., 2019

2018
BestSF: A Sparse Meta-Format for Optimizing SpMV on GPU.
ACM Trans. Archit. Code Optim., 2018

Power-aware high level evaluation model of interconnect length of on-chip memory network topology.
Int. J. Comput. Sci. Eng., 2018

A novel look-ahead routing algorithm based on graph theory for triplet-based network-on-chip router.
IEICE Electron. Express, 2018

An Efficient Distributed Minimal Routing Algorithm for Triplet-Based WK-recursive Network.
Proceedings of the 20th IEEE International Conference on High Performance Computing and Communications; 16th IEEE International Conference on Smart City; 4th IEEE International Conference on Data Science and Systems, 2018

2017
Exploring grouped coherence for clustered hierarchical cache.
J. Supercomput., 2017

An evaluation power model for TriBA based application mapping and memory-on-chip.
Proceedings of the 13th International Conference on Natural Computation, 2017

2016
Sparse Matrix Format Selection with Multiclass SVM for SpMV on GPU.
Proceedings of the 45th International Conference on Parallel Processing, 2016

Machine Learning Approach for the Predicting Performance of SpMV on GPU.
Proceedings of the 22nd IEEE International Conference on Parallel and Distributed Systems, 2016

Energy evaluation of Sparse Matrix-Vector Multiplication on GPU.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
Achieving self-aware parallelism in stream programs.
Clust. Comput., 2015

2014
Exploiting controlled-grained parallelism in message-driven stream programs.
J. Supercomput., 2014

An adaptive and hierarchical task scheduling scheme for multi-core clusters.
Parallel Comput., 2014

Optimal Pipeline Performance via Transactional Slice with No Branch Prediction Overhead.
Proceedings of the UKSim-AMSS 16th International Conference on Computer Modelling and Simulation, 2014

2013
A work-stealing scheduling framework supporting fault tolerance.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
A Hierarchical Work-Stealing Framework for Multi-core Clusters.
Proceedings of the 13th International Conference on Parallel and Distributed Computing, 2012

Knowledge-Based Adaptive Self-Scheduling.
Proceedings of the Network and Parallel Computing, 9th IFIP International Conference, 2012

Communication Locality Analysis of Triplet-Based Hierarchical Interconnection Network in Chip Multiprocessor.
Proceedings of the Network and Parallel Computing, 9th IFIP International Conference, 2012

2011
3D floorplanning of low-power and area-efficient Network-on-Chip architecture.
Microprocess. Microsystems, 2011

Dynamic and adaptive SPM management for a multi-task environment.
J. Syst. Archit., 2011

Core Working Set Based Scratchpad Memory Management.
IEICE Trans. Inf. Syst., 2011

2009
A Novel Adaptive Scratchpad Memory Management Strategy.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

N-port memory mapping for LUT-based FPGAs.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Group-caching for NoC based multicore cache coherent systems.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
An efficient layered data compression scheme with constraint analysis.
Math. Comput. Simul., 2008

2007
Performance Evaluation of a Self-Maintained Memory Module.
Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

THIN: A New Hierarchical Interconnection Network-on-Chip for SOC.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2007

A self-maintained memory module supporting DMM.
Proceedings of the 2007 International Conference on Compilers, 2007

A Triplet-based Computer Architecture Supporting Parallel Object Computing.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

The Design of a Novel Object-oriented Processor : OOMIPS.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
A Novel Image Compression Architecture with proficient Layered scenario.
Proceedings of the Sixth International Conference on Intelligent Systems Design and Applications (ISDA 2006), 2006


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