Feng Han

Affiliations:

Nanjing University, Institute of VLSI Design, School of Electronic Science and Engineering, China

According to our database¹, Feng Han authored at least 11 papers between 2014 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2017

Optimized sorting network for successive cancellation list decoding of polar codes.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

An access pattern based adaptive mapping function for GPGPU scratchpad memory.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Application space exploration of a multi-fabric reconfigurable system.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

Design and implementation of high performance matrix inversion based on reconfigurable processor.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

An ultra-long FFT architecture implemented in a reconfigurable application specified processor.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Floating-point operation based reconfigurable architecture for radar processing.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

Accurate runtime thermal prediction scheme for 3D NoC systems with noisy thermal sensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

An improved FFT architecture optimized for reconfigurable application specified processor.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

Lateral asynchronous and vertical synchronous 3D Network on Chip with double pumped vertical links.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A high performance parallel VLSI design of matrix inversion.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

A survey of memory architecture for 3D chip multi-processors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

Feng Han

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