Fen Ge

Orcid: 0009-0002-3162-8389

According to our database1, Fen Ge authored at least 53 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
A Lightweight BiSeNet Embedded with YOLOv5 Feature Fusion Network.
Proceedings of the 23rd IEEE International Conference on Communication Technology, 2023

A Deep Q Network Hardware Accelerator Based on Heterogeneous Computing.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Method of Mapping Convolutional Neural Networks on Resource-limited NoC Platform.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

A Multi-mode Convolution Coprocessor Based on RISC-V Instruction Set Architecture.
Proceedings of the 15th IEEE International Conference on ASIC, 2023

FPGA implementation and verification of efficient and reconfigurable CNN-LSTM accelerator design.
Proceedings of the 3rd Guangdong-Hong Kong-Macao Greater Bay Area Artificial Intelligence and Big Data Forum, 2023

2022
The Design of a Novel Hardware Trojan without Inactive Signal for AES.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

A Hybrid CNN Compression Approach for Hardware Acceleration.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

A Defense Method Against Persistent Fault Attack.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

A Vehicle Line-Pressing Detection Approach Based on YOLOv5 and DeepSort.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Efficient Configurable Digit-Serial Multiplier Based on Improved Karatsuba Algorithm over GF(2m).
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Implementation of Bidirectional LSTM Accelerator Based on FPGA.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

Reconfigurable Multi-algorithm Neural Network Accelerator Based on Target Detection.
Proceedings of the 22nd IEEE International Conference on Communication Technology, 2022

2021
Highly efficient architecture of elliptic curve scalar multiplication with fault tolerance over GF(2<sup>m</sup>).
IEICE Electron. Express, 2021

Collaborative thermal- and traffic-aware adaptive routing scheme for 3D network-on-chip systems.
IEICE Electron. Express, 2021

Implementation of Reconfigurable CNN-LSTM Accelerator Based on FPGA.
Proceedings of the 21st International Conference on Communication Technology, 2021

An Anti-DPA Elliptic Curve Cryptography Scalar Multiplier with Randomized Base Point.
Proceedings of the 21st International Conference on Communication Technology, 2021

Hardware Trojan Detection Method for Gate-Level Netlists Based on the Idea of Few-Shot Learning.
Proceedings of the 21st International Conference on Communication Technology, 2021

Design and Implementation of OpenCL-Based FPGA Accelerator for YOLOv2.
Proceedings of the 21st International Conference on Communication Technology, 2021

2020
Algorithm-Hardware Co-Design of Real-Time Edge Detection for Deep-Space Autonomous Optical Navigation.
IEICE Trans. Inf. Syst., 2020

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping.
IEICE Electron. Express, 2020

A Dynamic Branch Predictor Based on Parallel Structure of SRNN.
IEEE Access, 2020

Small Area Configurable Deep Neural Network Accelerator for IoT System.
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

A Mapping Method for Convolutional Neural Networks on Network-on-Chip.
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

Design and Implementation of LSTM Accelerator Based on FPGA.
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

Differential Fault Attack for the Iterative Operation of AES-192 Key Expansion.
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

A Scalable Bit-Parallel Word-Serial Multiplier with Fault Detection on GF(2^m).
Proceedings of the 20th IEEE International Conference on Communication Technology, 2020

2019
Machine learning-based dynamic reconfiguration algorithm for reconfigurable NoCs.
IEICE Electron. Express, 2019

RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs.
IEICE Electron. Express, 2019

Fault attack hardware Trojan detection method based on ring oscillator.
IEICE Electron. Express, 2019

Srax: A Low Crosstalk and Insertion Loss 5×5 Optical Router for Optical Network-on-Chip.
Proceedings of the IECON 2019, 2019

A dual-threshold credit-based flow control mechanism for 3D Network-on-Chip.
Proceedings of the International Conference on IC Design and Technology, 2019

2018
Countermeasure against fault sensitivity analysis based on clock check block.
IEICE Electron. Express, 2018

2017
Collaborative fuzzy-based partially-throttling dynamic thermal management scheme for three-dimensional networks-on-chip.
IET Comput. Digit. Tech., 2017

ArR-DTM: A routing-based DTM for 3D NoCs by adaptive degree regulation.
IEICE Electron. Express, 2017

Thermal-aware task mapping for communication energy minimization on 3D NoC.
IEICE Electron. Express, 2017

2016
Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Efficient Synchronization for Distributed Embedded Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Optimization of Area and Delay for Implementation of the Composite Field Advanced Encryption Standard S-Box.
J. Circuits Syst. Comput., 2016

A MapReduce architecture for embedded multiprocessor system-on-chips.
IEICE Electron. Express, 2016

MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints.
IEICE Electron. Express, 2016

2015
Distributed Synchronization for Message-Passing Based Embedded Multiprocessors.
IEICE Trans. Inf. Syst., 2015

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA.
IEICE Electron. Express, 2015

The Adaptive Thermal and Traffic-Balanced Routing algorithm based on temperature analysis and traffic statistics.
IEICE Electron. Express, 2015

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

DimNoC: a dim silicon approach towards power-efficient on-chip network.
Proceedings of the 52nd Annual Design Automation Conference, 2015

A network components insertion method for 3D application-specific Network-on-Chip.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Designing vertical bandwidth reconfigurable 3D NoCs for many core systems.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
A two-phase floorplanning approach for Application-specific Network-on-Chip.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
A Coverage-Driven Verification Platform for Evaluating NoC Performance and Test Structure.
Proceedings of the 26th International Conference on Advanced Information Networking and Applications Workshops, 2012

2009
Design of a GALS Wrapper for Network on Chip.
Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008
A minimum-path mapping algorithm for 2D mesh Network on Chip architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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