Felix Bürgin

According to our database1, Felix Bürgin authored at least 8 papers between 2005 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2008
Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Wireless Implant Communications for Biomedical Monitoring Sensor Network.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A 0.25 μm 0.92 mW per Mb/s Viterbi decoder featuring resonant clocking for ultra-low-power 54 Mb/s WLAN communication.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
42% power savings through glitch-reducing clocking strategy in a hearing aid application.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Two-phase resonant clocking for ultra-low-power hearing aid applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications.
Proceedings of the Integrated Circuit and System Design, 2005

A 0.67-mm<sup>2</sup> 45-μW DSP VLSI implementation of an adaptive directional microphone for hearing aids.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005


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