Felipe S. Marranghello

Raphael Martins Brum

Paulo F. Butzen

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021

LUT-Based Optimization For ASIC Design Flow.

[BibT_eX]

[DOI]

Luca Gaetano Amarù

Eleonora Testa

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

maj-n Logic Synthesis for Emerging Technology.

[BibT_eX]

[DOI]

Augusto Neutzling

Jody Maick Matos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Exact Benchmark Circuits for Logic Synthesis.

[BibT_eX]

[DOI]

Walter Lau Neto

Pierre-Emmanuel Gaillardon

Jody Maick Matos

Renato Perez Ribas

IEEE Des. Test, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

[BibT_eX]

[DOI]

Luca G. Amarù

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Four-Level Forms for Memristive Material Implication Logic.

[BibT_eX]

[DOI]

Vinicius Callegaro

IEEE Trans. Very Large Scale Integr. Syst., 2019

Threshold Physical Unclonable Functions.

[BibT_eX]

[DOI]

Yang Yu

Elena Dubrova

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

2018

One-Sided Countermeasures for Side-Channel Attacks Can Backfire.

[BibT_eX]

[DOI]

Yang Yu

Victor Diges Teijeira

Elena Dubrova

Proceedings of the 11th ACM Conference on Security & Privacy in Wireless and Mobile Networks, 2018

Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation.

[BibT_eX]

[DOI]

Walter Lau Neto

Jody Maick Matos

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

2017

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC.

[BibT_eX]

[DOI]

Vinícius Dal Bem

IEEE Trans. Emerg. Top. Comput., 2017

Binary adder circuit design using emerging MIGFET devices.

[BibT_eX]

[DOI]

Jeferson José Baqueta

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

2016

Performance evaluation of optimized transistor networks built using independent-gate FinFET.

[BibT_eX]

[DOI]

Andres M. A. Valdes

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

Factored Forms for Memristive Material Implication Stateful Logic.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Fast buffer delay estimation considering time-dependent dielectric breakdown.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Improved logic synthesis for memristive stateful logic using multi-memristor implication.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

SOP based logic synthesis for memristive IMPLY stateful logic.

[BibT_eX]

[DOI]

Vinicius Callegaro

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis.

[BibT_eX]

[DOI]

Vinicius Callegaro

Mayler G. A. Martins

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Enhanced Spin-Diode Synthesis Using Logic Sharing.

[BibT_eX]

[DOI]

Mayler G. A. Martins

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

CMOS inverter analytical delay model considering all operating regions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Spin diode network synthesis using functional composition.

[BibT_eX]

[DOI]

Mayler G. A. Martins

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Delay model for static CMOS complex gates.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

CMOS inverter delay model based on DC transfer curve for slow input.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Design-oriented delay model for CMOS inverter.

[BibT_eX]

[DOI]

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

2011

Transistor sizing in lithography-aware regular fabrics.

[BibT_eX]

[DOI]

Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Impact and optimization of lithography-aware regular layout in digital circuit design.

[BibT_eX]

[DOI]

Vinícius Dal Bem

Paulo F. Butzen

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Transistor Sizing Analysis of Regular Fabrics.

[BibT_eX]

[DOI]