Felipe S. Marques
Orcid: 0000-0003-1318-9992Affiliations:
- University of Pelotas, Technology Development Center, Brazil
- Federal University of Pelotas, Group ofArchitectures and Integrated Circuits, GACI, Brazil
- Nangate Inc
According to our database1,
Felipe S. Marques
authored at least 40 papers
between 2002 and 2022.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
On csauthors.net:
Bibliography
2022
2021
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling.
ACM Trans. Design Autom. Electr. Syst., 2021
2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the Sixteenth Mexican International Conference on Artificial Intelligence, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A post-processing methodology to improve the automatic design of CMOS gates at layout-level.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Topological characteristics of logic networks generated by a graph-based methodology.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform.
Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2008
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
2002
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002