Felice Balarin
According to our database1,
Felice Balarin
authored at least 62 papers
between 1992 and 2009.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Automatic buffer sizing for rate-constrained KPN applications on multiprocessor system-on-chip.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2007
2006
Int. J. Parallel Program., 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Functional verification methodology based on formal interface specification and transactor generation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
A formal approach to system level design: metamodels and unified design environments.
Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005
Proceedings of the 2005 Design, 2005
2004
Logic of constraints: a quantitative performance and functional constraint formalism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Des. Autom. Embed. Syst., 2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
Proceedings of the EMSOFT 2004, 2004
Proceedings of the 2004 Design, 2004
2003
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003
Proceedings of the Embedded Software for SoC, 2003
2002
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002
Proceedings of the Embedded Software, Second International Conference, 2002
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002
2001
Synchronous approach to the functional equivalence of embeddedsystem implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 7th IEEE Real-Time Technology and Applications Symposium (RTAS 2001), 30 May, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the First International Workshop on Symbolic Model Checking, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999
1998
Proceedings of the Languages, 1998
Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998
1997
Proceedings of the Second International Workshop on Verification of Infinite State Systems, 1997
Proceedings of the 34st Conference on Design Automation, 1997
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997
1996
Proceedings of the 17th IEEE Real-Time Systems Symposium (RTSS '96), 1996
Proceedings of the 33st Conference on Design Automation, 1996
1995
Formal Methods Syst. Des., 1995
Proceedings of the Computer Aided Verification, 1995
Proceedings of the Computer Aided Verification, 1995
1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 31st Conference on Design Automation, 1994
Proceedings of the Computer Aided Verification, 6th International Conference, 1994
1993
Verilog HDL Modeling Styles for Formal Verification.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
Proceedings of the Computer Aided Verification, 5th International Conference, 1993
1992
Proceedings of the Computer Aided Verification, Fourth International Workshop, 1992