Feifei Niu

Orcid: 0000-0002-4123-4554

According to our database1, Feifei Niu authored at least 12 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
An extensive replication study of the ABLoTS approach for bug localization.
Empir. Softw. Eng., November, 2024

What Makes a High-Quality Training Dataset for Large Language Models: A Practitioners' Perspective.
Proceedings of the 39th IEEE/ACM International Conference on Automated Software Engineering, 2024

RAT: A Refactoring-Aware Tool for Tracking Code History.
Proceedings of the 2024 IEEE/ACM 46th International Conference on Software Engineering: Companion Proceedings, 2024

2023
The ABLoTS Approach for Bug Localization: is it replicable and generalizable?
Proceedings of the 20th IEEE/ACM International Conference on Mining Software Repositories, 2023

RAT: A Refactoring-Aware Traceability Model for Bug Localization.
Proceedings of the 45th IEEE/ACM International Conference on Software Engineering, 2023

2022
Measuring Business Process Behavioral Similarity Based on Token Log Profile.
IEEE Trans. Serv. Comput., 2022

Design and Construction of a Superconducting Gravimeter Prototype.
IEEE Trans. Instrum. Meas., 2022

Towards Just-In-Time Feature Request Approval Prediction.
Proceedings of the Internetware 2022: 13th Asia-Pacific Symposium on Internetware, Hohhot, China, June 11, 2022

2021
Process Models for evaluating Process Similarity Algorithms.
Dataset, October, 2021

Cloud Technology Dual Data Center Information System Based on Disaster Recovery Platform.
Proceedings of the 2021 International Conference on Machine Learning and Big Data Analytics for IoT Security and Privacy, 2021

2015
Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2011
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011


  Loading...