Feida Wang
According to our database1,
Feida Wang
authored at least 2 papers
between 2023 and 2024.
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Bibliography
2024
A 0.55-mm<sup>2</sup> 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture.
Microelectron. J., February, 2024
2023
An 8-bit 1.5-GS/s Voltage-Time Hybrid Two-Step ADC With Cross-Coupled Linearized VTC.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023