Fei Yuan

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

A Cyclic Vernier Digital-to-Time Converter for Time-Mode Successive Approximation TDC.

[BibT_eX]

[DOI]

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

2022

Metastability Error Correction for True Single-Phase Clock DFF With Applications in Vernier TDC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter.

[BibT_eX]

[DOI]

Microelectron. J., 2022

All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Performance Limits of Gated Delay Line Time Integrators.

[BibT_eX]

[DOI]

Proceedings of the IEEE Canadian Conference on Electrical and Computer Engineering, 2022

2021

All-digital successive approximation TDC in time-mode signal processing.

[BibT_eX]

[DOI]

Microelectron. J., 2021

Adaptive data-transition decision feedback equaliser with edge emphasis.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2021

An 8-bit digital-to-time converter with pre-skewing and time interpolation.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2021

Bootstrapping Techniques for Energy-Efficient SAR ADCs : A State-of-the-Art Review.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Successive Approximation Register TDC in Time-Mode Signal Processing.

[BibT_eX]

[DOI]

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020

Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2020

All-digital power-efficient integrating frequency difference-to-digital converter for GHz frequency-locking.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2020

All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability.

[BibT_eX]

[DOI]

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

Sign<sup>3</sup>-LMS data-transition decision feedback equaliser.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2019

Data-Transition Decision Feedback Equalizer with Edge-Emphasis Taps and Raised References.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019

All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A 500-MS/s 8.4-ps Double-Edge Successive Approximation TDC in 65 nm CMOS.

[BibT_eX]

[DOI]

Rashed Siddiqui

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Pre-Skewed Bi-Directional Gated Delay Line Bang-Bang Frequency Detector with Applications in 10 Gbps Serial Link Frequency-Locking.

[BibT_eX]

[DOI]

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Digitally Interpolated Pre-Skewed Delay-Line Digital-to-Time Converter with Minimum Nonlinearity and Latency.

[BibT_eX]

[DOI]

Gul N. Khan

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator.

[BibT_eX]

[DOI]

Young Jun Park

Microelectron. J., 2018

Design techniques of all-digital arithmetic units for time-mode signal processing.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2018

Multi-Swarm based NoC Configuration and Synthesis.

[BibT_eX]

[DOI]

Muhammad Obaidullah

Gul N. Khan

Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Data-Transition Decision Feedback Equalizer with S<sup>3</sup>-LMS Adaptation Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

A Comparative Study Of Injection Locked Frequency Divider Using Harmonic Mixer In Weak And Strong Inversion.

[BibT_eX]

[DOI]

Jared Mercier

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Two-step pulse-shrinking time-to-digital converter.

[BibT_eX]

[DOI]

Young Jun Park

Microelectron. J., 2017

Adaptive 4PAM decision feedback equalizer with reduced number of slicers.

[BibT_eX]

[DOI]