Fei Xia

Orcid: 0000-0002-3426-8406

Affiliations:
  • Newcastle University, Newcastle upon Tyne, UK
  • King's College London, UK (PhD 2000)


According to our database1, Fei Xia authored at least 85 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2023
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption.
Integr., November, 2023

HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method.
IEEE Access, 2023

Variable Duty Cycle Pulse Generation for Low Complexity Randomization in Machine Learning.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Asynchronous Control for Tsetlin Machine with Binary Memristor-Transistor Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
Practical Distributed Implementation of Very Large Scale Petri Net Simulations.
Trans. Petri Nets Other Model. Concurr., 2022

Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Editable asynchronous control logic for SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Automated Synthesis of Asynchronous Tsetlin Machines on FPGA.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

Runtime Energy Minimization of Distributed Many-Core Systems using Transfer Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
QoS-Aware Power Minimization of Distributed Many-Core Servers using Transfer Q-Learning.
CoRR, 2021

Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems.
IEEE Trans. Computers, 2020

Amdahl's law in the context of heterogeneous many-core systems - a survey.
IET Comput. Digit. Tech., 2020

Dynamics of Time-Domain Power-Elastic Circuits for Pervasive Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding.
CoRR, 2019

Modelling Reversion Loss and Shoot-through Current in Switched-Capacitor DC-DC Converters with Petri Nets.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

2018
Speedup and Power Scaling Models for Heterogeneous Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

Modelling Switched-Capacitor DC-DC Converters with Signal Transition Graphs.
Proceedings of the 15th International Conference on Synthesis, 2018

Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2017
Voltage, Throughput, Power, Reliability, and Multicore Scaling.
Computer, 2017

Modelling for Systems with Holistic Fault Tolerance.
Proceedings of the Software Engineering for Resilient Systems - 9th International Workshop, 2017

Ultra-Low Energy Data Driven Computing Using Asynchronous Micropipelines and Nano-Electro-Mechanical Relays.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Speedup and Parallelization Models for Energy-Efficient Many-Core Systems Using Performance Counters.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Architecting Holistic Fault Tolerance.
Proceedings of the 18th IEEE International Symposium on High Assurance Systems Engineering, 2017

Selective Abstraction for Estimating Extra-Functional Properties in Networks-on-Chips Using ArchOn Framework.
Proceedings of the 17th International Conference on Application of Concurrency to System Design, 2017

2016
Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

A smart all-digital charge to digital converter.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Selective abstraction and stochastic methods for scalable power modelling of heterogeneous systems.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Low power voltage sensing through capacitance to digital conversion.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Fast capacitance-to-digital converter with internal reference.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing.
Proceedings of the 16th International Conference on Application of Concurrency to System Design, 2016

2015
A Formal Specification and Prototyping Language for Multi-core System Management.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Wideband dynamic voltage sensing mechanism for EH systems.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

An elastic timer for wide dynamic working range.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Order Graphs and Cross-Layer Parametric Significance-Driven Modelling.
Proceedings of the 15th International Conference on Application of Concurrency to System Design, 2015

2014
Modeling and Tools for Power Supply Variations Analysis in Networks-on-Chip.
IEEE Trans. Computers, 2014

Asynchronously assisted FPGA for variability.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Asynchronous design for new on-chip wide dynamic range power electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

ArchOn: Architecture-open Resource-driven Cross-layer Modelling Framework.
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014

Studying the Interplay of Concurrency, Performance, Energy and Reliability with ArchOn - An Architecture-Open Resource-Driven Cross-Layer Modelling Framework.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013
Dynamic programming-based runtime thermal management (DPRTM): An online thermal control strategy for 3D-NoC systems.
ACM Trans. Design Autom. Electr. Syst., 2013

Concurrent Multiresource Arbiter: Design and Applications.
IEEE Trans. Computers, 2013

Hybrid wire-surface wave interconnects for next-generation networks-on-chip.
IET Comput. Digit. Tech., 2013

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip.
Comput. J., 2013

Wide-range, reference free, on-chip voltage sensor for variable Vdd operations.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip.
IEEE Trans. Parallel Distributed Syst., 2012

Towards power-elastic systems through concurrency management.
IET Comput. Digit. Tech., 2012

A hybrid power delivery method for asynchronous loads in energy harvesting systems.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Ultra-low power transmitter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Minimizing power supply noise through harmonic mappings in networks-on-chip.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Self-Timed SRAM for Energy Harvesting Systems.
J. Low Power Electron., 2011

A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems.
ACM J. Emerg. Technol. Comput. Syst., 2011

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Improving the Robustness of Self-timed SRAM to Variable Vdds.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Variation tolerant asynchronous FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Run-time deadlock detection in networks-on-chip using coupled transitive closure networks.
Proceedings of the Design, Automation and Test in Europe, 2011

Variation Tolerant AFPGA Architecture.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
Highly parallel multi-resource arbiters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Asynchronous FPGA architecture with distributed control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Stochastic analysis of power, latency and the degree of concurrency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Fine-grain stochastic modelling of dynamic power management policies and analysis of their power - latency tradeoffs.
IET Softw., 2009

The Magic Rule of Tiles: Virtual Delay Insensitivity.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Modular Approach to Multi-resource Arbiter Design.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2007
Automating Synthesis of Asynchronous Communication Mechanisms.
Fundam. Informaticae, 2007

Asynchronous Functional Coupling for Low Power Sensor Network Processors.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Compositional Method for the Synthesis of Asynchronous Communication Mechanisms.
Proceedings of the Petri Nets and Other Models of Concurrency, 2007

The Design of Virtual Self-timed Block for Activity Communication in SOC.
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006
Buffered Asynchronous Communication Mechanisms.
Fundam. Informaticae, 2006

Virtual self-timed blocks for systems-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Low-Cost Online Testing of Asynchronous Handshakes.
Proceedings of the 11th European Test Symposium, 2006

2004
MATLAB Models of ACMS in Control Systems.
Proceedings of the ICINCO 2004, 2004

2002
Data Communication in Systems with Heterogeneous Timing.
IEEE Micro, 2002

Algorithms for Signal and Message Asynchronous Communication Mechanisms and their Analysis.
Fundam. Informaticae, 2002

Asynchronous circuit synthesis via direct translation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
Supporting the MASCOT method with Petri net techniques for real-time systems development.
PhD thesis, 2000

Asynchronous Communication Mechanisms Using Self-Timed Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998
Towards Asynchronous A-D Conversion.
Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March, 1998

1995
Evaluation of the Data Interaction Architecture Demonstrator by means of a multiple mobile robot workspace simulation.
Microprocess. Microsystems, 1995

1994
A Parallel Simulation of Multiple Mobile Robots Using the DORIS Design Method.
Proceedings of the 1994 International Conference on Robotics and Automation, 1994


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