Fei Wu

Orcid: 0000-0001-9746-4714

Affiliations:
  • Huazhong University of Science and Technology, Key Lab of Data Storage Systems, Wuhan, China
  • Wuhan National Laboratory for Optoelectronics, Wuhan, China


According to our database1, Fei Wu authored at least 91 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2024
Improving DRAM Reliability Using a High Order Error Correction Code.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

TieredHM: Hotspot-Optimized Hash Indexing for Memory-Semantic SSD-Based Hybrid Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

An SR-IOV SSD Optimized for QoS-Sensitive IaaS Cloud Storage.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

HA-CSD: Host and SSD Coordinated Compression for Capacity and Performance.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

LaVA: An Effective Layer Variation Aware Bad Block Management for 3D CT NAND Flash.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Balloon-ZNS: Constructing High-Capacity and Low-Cost ZNS SSDs with Built-in Compression.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Eliminating Storage Management Overhead of Deduplication over SSD Arrays Through a Hardware/Software Co-Design.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Exploiting the Single-Symbol LLR Variation to Accelerate LDPC Decoding for 3-D nand Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Pipette: Efficient Fine-Grained Reads for SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Holistic and Opportunistic Scheduling of Background I/Os in Flash-Based SSDs.
IEEE Trans. Computers, November, 2023

High-Precision Short-Term Lifetime Prediction in TLC 3-D NAND Flash Memory as Hot-Data Storage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023

eLDPC: An Efficient LDPC Coding Scheme for Phase-Change Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Exploiting Metadata to Estimate Read Reference Voltage for 3-D nand Flash Memory.
IEEE Trans. Consumer Electron., February, 2023

ALCod: Adaptive LDPC Coding for 3-D NAND Flash Memory Using Inter-Layer RBER Variation.
IEEE Trans. Consumer Electron., 2023

ADT-FSE: A New Encoder for SZ.
Proceedings of the International Conference for High Performance Computing, 2023

FlexZNS: Building High-Performance ZNS SSDs with Size-Flexible and Parity-Protected Zones.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

2022
Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory.
ACM Trans. Storage, 2022

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision.
ACM Trans. Design Autom. Electr. Syst., 2022

Understanding and Exploiting the Full Potential of SSD Address Remapping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

WA-OPShare: Workload-Adaptive Over-Provisioning Space Allocation for Multi-Tenant SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Optimal Program-Read Schemes Toward Highly Reliable Open Block Operations in 3-D Charge-Trap NAND Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PACA: A Page Type Aware Read Cache Scheme in QLC Flash-based SSDs.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Error Generation for 3D NAND Flash Memory.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Work-in-Progress: High-Precision Short-Term Lifetime Prediction in TLC 3D NAND Flash Memory as Hot-data Storage.
Proceedings of the International Conference on Compilers, 2022

Tiered Hashing: Revamping Hash Indexing under a Unified Memory-Storage Hierarchy.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
LiveSSD: A Low-Interference RAID Scheme for Hardware Virtualized SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

An Efficient Data Migration Scheme to Optimize Garbage Collection in SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

DEPS: Exploiting a Dynamic Error Prechecking Scheme to Improve the Read Performance of SSD.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Write-Optimized B<sup>+</sup> Tree Index Technology for Persistent Memory.
J. Comput. Sci. Technol., 2021

Seer-SSD: Bridging Semantic Gap between Log-Structured File Systems and SSDs to Reduce SSD Write Amplification.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Intelligent Prediction of Flash Lifetime via Online Domain Adaptation.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Remap-SSD: Safely and Efficiently Exploiting SSD Address Remapping to Eliminate Duplicate Writes.
Proceedings of the 19th USENIX Conference on File and Storage Technologies, 2021

SW-WAL: Leveraging Address Remapping of SSDs to Achieve Single-Write Write-Ahead Logging.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Using Error Modes Aware LDPC to Improve Decoding Performance of 3-D TLC NAND Flash.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

BlockHammer: Improving Flash Reliability by Exploiting Process Variation Aware Proactive Failure Prediction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

LUDA: Boost LSM Key Value Store Compactions with GPUs.
CoRR, 2020

Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database.
Proceedings of the IEEE/ACM Workshop on Memory Centric High Performance Computing, 2020

Disperse Access Considered Energy Inefficiency in Intel Optane DC Persistent Memory Servers.
Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020

BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Pair-Bit Errors Aware LDPC Decoding in MLC NAND Flash Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

SCORE: A Novel Scheme to Efficiently Cache Overlong ECCs in NAND Flash Memory.
ACM Trans. Archit. Code Optim., 2019

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory.
IEEE Access, 2019

VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

RAFS: A RAID-Aware File System to Reduce the Parity Update Overhead for SSD RAID.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

WAS: Wear Aware Superblock Management for Prolonging SSD Lifetime.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Characterizing 3D Floating Gate NAND Flash: Observations, Analyses, and Implications.
ACM Trans. Storage, 2018

WARD: Wear Aware RAID Design Within SSDs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory.
IEEE Access, 2018

Exploiting Minipage-Level Mapping to Improve Write Efficiency of NAND Flash.
Proceedings of the 2018 IEEE International Conference on Networking, 2018

Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and Applications.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read Performance.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

HODS: Hardware Object Deserialization Inside SSD Storage.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Program error rate-based wear leveling for NAND flash memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDs.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Understanding and Alleviating the Impact of the Flash Address Translation on Solid State Devices.
ACM Trans. Storage, 2017

Building Efficient Key-Value Stores via a Lightweight Compaction Tree.
ACM Trans. Storage, 2017

A Program Interference Error Aware LDPC Scheme for Improving NAND Flash Decoding Performance.
ACM Trans. Embed. Comput. Syst., 2017

Extending Real-Time Analysis for Wormhole NoCs.
IEEE Trans. Computers, 2017

一种固态盘的读写性能优化调度方法 (Read-Write Performance Optimization Scheduling Scheme for SSD).
计算机科学, 2017

Modeling recommender systems via weighted bipartite network.
Concurr. Comput. Pract. Exp., 2017

Characterizing 3D Floating Gate NAND Flash.
Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, Urbana-Champaign, IL, USA, June 05, 2017

ALARM: A Location-Aware Redistribution Method to Improve 3D FG NAND Flash Reliability.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

OptiMatch: Enabling an Optimal Match between Green Power and Various Workloads for Renewable-Energy Powered Storage Systems.
Proceedings of the 46th International Conference on Parallel Processing, 2017

CooECC: A Cooperative Error Correction Scheme to Reduce LDPC Decoding Latency in NAND Flash.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

FPGA-based failure mode testing and analysis for MLC NAND flash memory.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Lifetime adaptive ECC in NAND flash page management.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Alert-and-transfer: an evolutionary architecture for SSD-based storage systems.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

A Concurrent Skip List Balanced on Search.
Proceedings of the Advanced Parallel Processing Technologies, 2017

2016
TEES: A novel multiple criteria optimization scheme for temperature-constrained energy efficient storage.
J. Parallel Distributed Comput., 2016

Determining Image Base of Firmware Files for ARM Devices.
IEICE Trans. Inf. Syst., 2016

REAL: A retention error aware LDPC decoding scheme to improve NAND flash read performance.
Proceedings of the 32nd Symposium on Mass Storage Systems and Technologies, 2016

Leveraging Semantic Links for High Efficiency Page-Level FTL Design.
Proceedings of the 36th IEEE International Conference on Distributed Computing Systems Workshops, 2016

MRAMsim: A Simulator for Magnetoresistive RAM.
Proceedings of the 36th IEEE International Conference on Distributed Computing Systems Workshops, 2016

Error behaviors testing with temperature and magnetism dependency for MRAM.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Real-Time Analysis for Wormhole NoC: Revisited and Revised.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
The information hiding mechanism based on compressed document format.
Int. J. Comput. Sci. Math., 2015

On the Cooling of Energy Efficient Storage.
Proceedings of the 10th IEEE International Conference on Networking, 2015

A novel optimization algorithm for Chien search of BCH Codes in NAND flash memory devices.
Proceedings of the 10th IEEE International Conference on Networking, 2015

An efficient page-level FTL to optimize address translation in flash memory.
Proceedings of the Tenth European Conference on Computer Systems, 2015

2014
sJournal: A New Design of Journaling for File Systems to Provide Crash Consistency.
Proceedings of the 9th IEEE International Conference on Networking, 2014

2013
Measuring and Analyzing Write Amplification Characteristics of Solid State Disks.
Proceedings of the 2013 IEEE 21st International Symposium on Modelling, 2013

Revisiting Behavior Amplification of NAND Flash-Based Storage Devices in Embedded Systems.
Proceedings of the IEEE 11th International Conference on Dependable, 2013

2012
INBI: An Improved Network-Based Inference Recommendation Algorithm.
Proceedings of the Seventh IEEE International Conference on Networking, 2012

2011
MIND: A black-box energy consumption model for disk arrays.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Analysis of the File System and Block IO Scheduler for SSD in Performance and Energy Consumption.
Proceedings of the 2011 IEEE Asia-Pacific Services Computing Conference, 2011

2010
A Low Cost and Inner-round Pipelined Design of ECB-AES-256 Crypto Engine for Solid State Disk.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

Cache Blocks: An Efficient Scheme for Solid State Drives without DRAM Cache.
Proceedings of the Fifth International Conference on Networking, Architecture, and Storage, 2010

TRACER: A Trace Replay Tool to Evaluate Energy-Efficiency of Mass Storage Systems.
Proceedings of the 2010 IEEE International Conference on Cluster Computing, 2010


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