Fei Lyu
Orcid: 0000-0003-2282-1574Affiliations:
- Jinling Institute of Technology, School of Electronics and Information Engineering, Nanjing, China
- Nanjing University, School of Electric Science and Engineering, China (PhD 2017)
According to our database1,
Fei Lyu
authored at least 13 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
FDM: Fused Double-Multiply Design for Low-Latency and Area- and Power-Efficient Implementation.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2022
High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers.
IEEE Trans. Very Large Scale Integr. Syst., 2022
ML-PLAC: Multiplierless Piecewise Linear Approximation for Nonlinear Function Evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEICE Electron. Express, 2022
Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2018
Sensors, 2018
2016
Influences of an Aluminum Covering Layer on the Performance of Cross-Like Hall Devices.
Sensors, 2016
2015
Sensors, 2015
2014
A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014