Fazal Hameed

According to our database, Fazal Hameed authored at least 32 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Efficient Memory Layout for Pre-Alignment Filtering of Long DNA Reads Using Racetrack Memory.

Asif Ali Khan, Fazal Hameed, Taha Shahroodi, Alex K. Jones, Jerónimo Castrillón

IEEE Comput. Archit. Lett., 2024

2023

DownShift: Tuning Shift Reduction With Reliability for Racetrack Memories.

Asif Ali Khan, Sébastien Ollivier, Fazal Hameed, Jerónimo Castrillón, Alex K. Jones

IEEE Trans. Computers, September, 2023

ROLLED: Racetrack Memory Optimized Linear Layout and Efficient Decomposition of Decision Trees.

Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, Jian-Jia Chen

IEEE Trans. Computers, May, 2023

An energy-efficient cache replacement policy for ultra-dense racetrack memory.

Fazal Hameed, Moazam Maqsood, Syed Ali Irtaza

J. Syst. Archit., April, 2023

2022

ALPHA: A Novel Algorithm-Hardware Co-Design for Accelerating DNA Seed Location Filtering.

Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón

IEEE Trans. Emerg. Top. Comput., 2022

BlendCache: An Energy and Area Efficient Racetrack Last-Level-Cache Architecture.

Fazal Hameed, Jerónimo Castrillón

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DNA Pre-Alignment Filter Using Processing Near Racetrack Memory.

Fazal Hameed, Asif Ali Khan, Sébastien Ollivier, Alex K. Jones, Jerónimo Castrillón

IEEE Comput. Archit. Lett., 2022

2021

Improving the Performance of Block-based DRAM Caches Via Tag-Data Decoupling.

Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón

IEEE Trans. Computers, 2021

BLOwing Trees to the Ground: Layout Optimization of Decision Trees on Racetrack Memory.

Christian Hakert, Asif Ali Khan, Kuan-Hsun Chen, Fazal Hameed, Jerónimo Castrillón, Jian-Jia Chen

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Optimizing Tensor Contractions for Embedded Devices with Racetrack and DRAM Memories.

Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón

ACM Trans. Embed. Comput. Syst., 2020

ShiftsReduce: Minimizing Shifts in Racetrack Memory 4.0.

Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón

ACM Trans. Archit. Code Optim., 2020

Magnetic Racetrack Memory: From Physics to the Cusp of Applications Within a Decade.

Robin Bläsing, Asif Ali Khan, Panagiotis Ch. Filippou, Chirag Garg, Fazal Hameed, Jerónimo Castrillón, Stuart S. P. Parkin

Proc. IEEE, 2020

Generalized Data Placement Strategies for Racetrack Memories.

Asif Ali Khan, Andrés Goens, Fazal Hameed, Jerónimo Castrillón

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement.

Fazal Hameed, Jerónimo Castrillón

IEEE Trans. Very Large Scale Integr. Syst., 2019

RTSim: A Cycle-Accurate Simulator for Racetrack Memories.

Asif Ali Khan, Fazal Hameed, Robin Bläsing, Stuart S. P. Parkin, Jerónimo Castrillón

IEEE Comput. Archit. Lett., 2019

Optimizing tensor contractions for embedded devices with racetrack memory scratch-pads.

Asif Ali Khan, Norman A. Rink, Fazal Hameed, Jerónimo Castrillón

Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory.

Joonas Multanen, Pekka Jääskeläinen, Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

Performance and Energy-Efficient Design of STT-RAM Last-Level Cache.

Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón

IEEE Trans. Very Large Scale Integr. Syst., 2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

NVMain Extension for Multi-Level Cache Systems.

Asif Ali Khan, Fazal Hameed, Jerónimo Castrillón

Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2018

2017

Efficient STT-RAM last-level-cache architecture to replace DRAM cache.

Fazal Hameed, Christian Menard, Jerónimo Castrillón

Proceedings of the International Symposium on Memory Systems, 2017

Rethinking on-chip DRAM cache for simultaneous performance and energy optimization.

Fazal Hameed, Jerónimo Castrillón

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction.

Fazal Hameed, Lars Bauer, Jörg Henkel

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Architecting STT Last-Level-Cache for performance and energy improvement.

Fazal Hameed, Mehdi Baradaran Tahoori

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches.

Fabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi, Mehdi Baradaran Tahoori

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

2015

DRAM Aware Last-Level-Cache Policies for Multi-core Systems.

Fazal Hameed

PhD thesis, 2015

2014

Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture.

Fazal Hameed, Lars Bauer, Jörg Henkel

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores.

Fazal Hameed, Lars Bauer, Jörg Henkel

Proceedings of the Design, Automation and Test in Europe, 2013

Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache.

Fazal Hameed, Lars Bauer, Jörg Henkel

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies.

Fazal Hameed, Lars Bauer, Jörg Henkel

Proceedings of the International Conference on Compilers, 2013

2012

Dynamic cache management in multi-core architectures through run-time adaptation.

Fazal Hameed, Lars Bauer, Jörg Henkel

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Dynamic thermal management in 3D multi-core architecture through run-time adaptation.

Fazal Hameed, Mohammad Abdullah Al Faruque, Jörg Henkel

Proceedings of the Design, Automation and Test in Europe, 2011