Fayez Gebali
Orcid: 0000-0001-5189-3409
According to our database1,
Fayez Gebali
authored at least 126 papers
between 2002 and 2024.
Collaborative distances:
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Bibliography
2024
Advanced security framework for low Earth orbit satellites in space information network.
EURASIP J. Wirel. Commun. Netw., December, 2024
Symmetry-Enabled Resource-Efficient Systolic Array Design for Montgomery Multiplication in Resource-Constrained MIoT Endpoints.
Symmetry, June, 2024
2023
Vision transformer architecture and applications in digital health: a tutorial and survey.
Vis. Comput. Ind. Biomed. Art, December, 2023
PUFGuard: Vehicle-to-Everything Authentication Protocol for Secure Multihop Mobile Communication.
Comput., October, 2023
Ensemble Siamese Network (ESN) Using ECG Signals for Human Authentication in Smart Healthcare System.
Sensors, 2023
ZTCloudGuard: Zero Trust Context-Aware Access Management Framework to Avoid Misuse Cases in the Era of Generative AI and Cloud-based Health Information Ecosystem.
CoRR, 2023
IEEE Access, 2023
2022
Compact Finite Field Multiplication Processor Structure for Cryptographic Algorithms in IoT Devices with Limited Resources.
Sensors, 2022
Sensors, 2022
Compact modular multiplier design for strong security capabilities in resource-limited Telehealth IoT devices.
J. King Saud Univ. Comput. Inf. Sci., 2022
2021
A Novel Framework for Combining Multiple Radar Waveforms Using Time Compression Overlap-Add.
IEEE Trans. Signal Process., 2021
Sustain. Comput. Informatics Syst., 2021
Internet Things, 2021
2020
Performance Analysis of Multiuser FSO/RF Network Under Non-Equal Priority With $P$ -Persistence Protocol.
IEEE Trans. Wirel. Commun., 2020
Expanding Window Dynamic-Programming-Based Track-Before-Detect With Order Statistics in Weibull Distributed Clutter.
IEEE Trans. Aerosp. Electron. Syst., 2020
Internet Things, 2020
Proceedings of the Advances in Networked-Based Information Systems, 2020
COVID-19-FAKES: A Twitter (Arabic/English) Dataset for Detecting Misleading Information on COVID-19.
Proceedings of the Advances in Intelligent Networking and Collaborative Systems - The 12th International Conference on Intelligent Networking and Collaborative Systems (INCoS-2020), Victoria, BC, Canada, 31 August, 2020
Proceedings of the Advanced Information Networking and Applications, 2020
Proceedings of the Handbook of Big Data Privacy., 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Consumer Electron., 2019
Low-Complexity Scalable Architectures for Parallel Computation of Similarity Measures.
Sci. Program., 2019
Decimator systolic arrays design space exploration for multirate signal processing applications.
IET Circuits Devices Syst., 2019
IET Circuits Devices Syst., 2019
Efficient parallel semi-systolic array structure for multiplication and squaring in GF(2<i><sup>m</sup></i>).
IEICE Electron. Express, 2019
Future Gener. Comput. Syst., 2019
A Novel Smeared Synthesized LFM TC-OLA Radar System: Design and Performance Evaluation.
IEEE Access, 2019
Fast Large Integer Modular Addition in GF(p) Using Novel Attribute-Based Representation.
IEEE Access, 2019
High Performance Implementation of Nested Array Beamformer for Wideband Radar Applications.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Proceedings of the IEEE Pacific Rim Conference on Communications, 2019
Proceedings of the IEEE International Conference on Consumer Electronics, 2019
Implementation of High Speed and Low Area Extended Euclidean Inversion over Ternary Fields.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019
Proceedings of the Web, Artificial Intelligence and Network Applications, 2019
A Novel Approach for Selecting Hybrid Features from Online News Textual Metadata for Fake News Detection.
Proceedings of the Advances on P2P, Parallel, Grid, Cloud and Internet Computing, 2019
2018
IEICE Electron. Express, 2018
IEEE Access, 2018
2017
Design Space Exploration of 2-D Processor Array Architectures for Similarity Distance Computation.
IEEE Trans. Parallel Distributed Syst., 2017
Scalable and Unified Digit-Serial Processor Array Architecture for Multiplication and Inversion Over GF( $2^{m}$ ).
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
Comput. Electr. Eng., 2017
On Time Compression Overlap-Add Technique in Linear Frequency Modulation Pulse Compression Radar Systems: Design and Performance Evaluation.
IEEE Access, 2017
Enhancement of time compression overlap-add using multirate downsample upsample shift add algorithm.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
Performance evaluation of time compression overlap-add radar systems based on order-statistics CFAR under convolution noise jamming.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
Proceedings of the IEEE Pacific Rim Conference on Communications, 2017
Proceedings of the IEEE International Conference on Communications, 2017
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction.
J. Signal Process. Syst., 2016
Low space-complexity and low power semi-systolic multiplier architectures over GF(2<sup>m</sup>) based on irreducible trinomial.
Microprocess. Microsystems, 2016
Microprocess. Microsystems, 2016
IEEE Commun. Lett., 2016
Efficient Scalable Digit-Serial Inverter Over GF( $2^{m}$ ) for Ultra-Low Power Devices.
IEEE Access, 2016
Dual-Hop VLC/RF Transmission System with Energy Harvesting Relay under Delay Constraint.
Proceedings of the 2016 IEEE Globecom Workshops, Washington, DC, USA, December 4-8, 2016, 2016
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016
Proceedings of the 30th IEEE International Conference on Advanced Information Networking and Applications, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Microelectron. J., 2015
IEEE Commun. Lett., 2015
Proceedings of the IEEE International Conference on Teaching, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Traffic analysis of multi-core body sensor networks based on Wireless NoC infrastructure.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Performance analysis of 64-bit Carry Lookahead Adders using conventional and hierarchical structure styles.
Proceedings of the IEEE Pacific Rim Conference on Communications, 2015
Proceedings of the IEEE International Conference on Ubiquitous Wireless Broadband, 2015
Proceedings of the 2015 IEEE Globecom Workshops, San Diego, CA, USA, December 6-10, 2015, 2015
2014
Inf. Sci., 2014
SMARTs: A Tool to Simulate and Analyze the Performance of Real-time Multi-core Systems.
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014
Proceedings of the 9th International Conference on Future Networks and Communications (FNC'14) / The 11th International Conference on Mobile Systems and Pervasive Computing (MobiSPC'14) / Affiliated Workshops, 2014
2013
Microprocess. Microsystems, 2013
IET Comput. Digit. Tech., 2013
2012
DSDMAC: Dual Sensing Directional MAC Protocol for Ad Hoc Networks with Directional Antennas.
IEEE Trans. Veh. Technol., 2012
Proceedings of the 2012 Seventh International Conference on Broadband, 2012
Proceedings of the 2012 Seventh International Conference on Broadband, 2012
2011
Processor Array Architectures for Scalable Radix 4 Montgomery Modular Multiplication Algorithm.
IEEE Trans. Parallel Distributed Syst., 2011
Int. J. Circuit Theory Appl., 2011
New processor array architecture for scalable radix 8 montgomery modular multiplication algorithm.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Performance-optimized FPGA implementation for the flexible triangle search block-based motion estimation algorithm.
Proceedings of the 24th Canadian Conference on Electrical and Computer Engineering, 2011
Proceedings of the 2011 International Conference on Broadband, 2011
2010
CoRR, 2010
Proceedings of the 72nd IEEE Vehicular Technology Conference, 2010
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2010
Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Networks-on-chip topology optimization subject to power, delay, and reliability constraints.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Power optimization for application-specific networks-on-chips: A topology-based approach.
Microprocess. Microsystems, 2009
J. Netw. Comput. Appl., 2009
Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification.
Comput. Networks, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
Proceedings of the 7th Annual Conference on Communication Networks and Services Research, 2009
Analytical modelling and performance analysis forwireless ad-hoc networks using four-way handshaking mechanism.
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009
Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, 2009
2008
Corrections to "Design and Performance Analysis of a Unified, Reconfigurable HMAC-Hash Unit" [Dec 07 2683-2695].
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Prioritized e-mail servicing to reduce non-spam delay and loss: A performance analysis.
Int. J. Netw. Manag., 2008
Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation.
IET Comput. Digit. Tech., 2008
J. Res. Pract. Inf. Technol., 2008
Proceedings of the 68th IEEE Vehicular Technology Conference, 2008
Quality of service support and backoff strategies in wireless networks with error control protocol.
Proceedings of the 3rd ACM Workshop on Performance Monitoring and Measurement of Heterogeneous Wireless and Wired Networks, 2008
Quality of service support in wireless local area network with error control protocol.
Proceedings of the LCN 2008, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Application-specific networks-on-chip topology customization using network partitioning.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
J. Circuits Syst. Comput., 2007
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007
2006
IEEE Trans. Parallel Distributed Syst., 2006
Multidimens. Syst. Signal Process., 2006
A New Analytical Model for Computing Blocking Probability in Optical Burst Switching Networks.
IEEE J. Sel. Areas Commun., 2006
Eur. Trans. Telecommun., 2006
An FPGA implementation of the flexible triangle search algorithm for block based motion estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006
2005
Markov chain analysis of collaborative codes in random multi access communication systems.
Comput. Commun., 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
2004
Proceedings of IEEE International Conference on Communications, 2004
2002
The JAFARDD processor: a Java architecture based on a Folding Algorithm, with Reservation stations, Dynamic translation, and Dual processing.
IEEE Trans. Consumer Electron., 2002