Fatemeh Serajeh-hassani

According to our database, Fatemeh Serajeh-hassani authored at least 3 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

An Efficient FPGA Architecture with Turn-Restricted Switch Boxes.

Fatemeh Serajeh-hassani, Mohammad Sadrosadati, Nezam Rohbani, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad

ACM Trans. Design Autom. Electr. Syst., May, 2024

2023

Designing a one-bit coplanar QCA ALU using a novel robust area-efficient three-input majority gate design.

Samira Riki, Fatemeh Serajeh-hassani

J. Supercomput., November, 2023

2019

Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch Boxes.

Fatemeh Serajeh-hassani, Mohammad Sadrosadati, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019