Farzin Karimi

According to our database1, Farzin Karimi authored at least 10 papers between 2001 and 2008.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
Applications of decorator and observer design patterns in functional verification.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

2004
Using data compression in automatic test equipment for system-on-chip testing.
IEEE Trans. Instrum. Meas., 2004

2003
Parallel testing of multi-port static random access memories.
Microelectron. J., 2003

Hybrid Multisite Testing at Manufacturing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
Random Testing of Multi-Port Static Random Access Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

A Scan-Bist Environment for Testing Embedded Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Data Compression for System-on-Chip Testing Using ATE.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Fault Detection in a Tristate System Environment.
IEEE Micro, 2001

A Parallel Approach for Testing Multi-Port Static Random Access Memories.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Parallel Testing of Multi-port Static Random Access Memories for BIST.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001


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