Farzaneh Zokaee

Orcid: 0000-0002-2080-1724

According to our database1, Farzaneh Zokaee authored at least 13 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Sky-Sorter: A Processing-in-Memory Architecture for Large-Scale Sorting.
IEEE Trans. Computers, February, 2023

2021
A High Performance, Multi-Bit Output Logic-in-Memory Adder.
IEEE Trans. Emerg. Top. Comput., 2021

FeFET-based Process-in-Memory Architecture for Low-Power DNN Training.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

EXMA: A Genomics Accelerator for Exact-Matching.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

2020
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory Architecture.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs.
IEEE Comput. Archit. Lett., 2018

2017
Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

A novel SAT-based ATPG approach for transition delay faults.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

2013
A new structure for interconnect offline testing.
Proceedings of the East-West Design & Test Symposium, 2013


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