Farzaneh Zokaee
Orcid: 0000-0002-2080-1724
According to our database1,
Farzaneh Zokaee
authored at least 13 papers
between 2013 and 2023.
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Bibliography
2023
IEEE Trans. Computers, February, 2023
2021
IEEE Trans. Emerg. Top. Comput., 2021
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021
SMART: A Heterogeneous Scratchpad Memory Architecture for Superconductor SFQ-based Systolic CNN Accelerators.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
2020
Mitigating Voltage Drop in Resistive Memories by Dynamic RESET Voltage Regulation and Partition RESET.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
LightBulb: A Photonic-Nonvolatile-Memory-based Accelerator for Binarized Convolutional Neural Networks.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
FindeR: Accelerating FM-Index-Based Exact Pattern Matching in Genomic Sequences through ReRAM Technology.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019
2018
IEEE Comput. Archit. Lett., 2018
2017
Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017
2013
Proceedings of the East-West Design & Test Symposium, 2013