Farzan Jazaeri

Orcid: 0000-0001-9649-3572

According to our database1, Farzan Jazaeri authored at least 14 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
Noise-Aware FET Circuit Design Based on C/I<sub>D</sub>-Invariant.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

2022
Tunneling Current Through a Double Quantum Dots System.
IEEE Access, 2022

Cryogenic RF Characterization and Simple Modeling of a 22 nm FDSOI Technology.
Proceedings of the 52nd IEEE European Solid-State Device Research Conference, 2022

2021
Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2019
A Review on Quantum Computing: From Qubits to Front-end Electronics and Cryogenic MOSFET Physics.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Cryogenic MOSFET Threshold Voltage Model.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
A Compact Model for Static and Dynamic Operation of Symmetric Double-Gate Junction FETs.
Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017
Total ionizing dose effects on analog performance of 28 nm bulk MOSFETs.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Negative capacitance field effect transistors; capacitance matching and non-hysteretic operation.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016
Impact of GigaRad Ionizing Dose on 28 nm bulk MOSFETs for future HL-LHC.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015
FOSS EKV 2.6 parameter extractor.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

2013
Heavily doped junctionless vertical slit FETs with slit width Below 20 nm.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013

Design space of twin gate junctionless vertical slit field effect transistors.
Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems, 2013


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