Farzan Fallah
According to our database1,
Farzan Fallah
authored at least 56 papers
between 1998 and 2014.
Collaborative distances:
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Bibliography
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2009
Low-Power Fanout Optimization Using Multi Threshold Voltages and Multi Channel Lengths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
2007
J. VLSI Signal Process., 2007
A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
2006
Optimizing Polynomial Expressions by Algebraic Factorization and Common Subexpression Elimination.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEICE Trans. Electron., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Analysis and Optimization of Static Power Considering Transition Dependency of Leakage Current in VLSI Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
A cache-defect-aware code placement algorithm for improving the performance of processors.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Common Subexpression Elimination Involving Multiple Variables for Linear DSP Synthesis.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Event-driven observability enhanced coverage analysis of C programs for functional validation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Functional vector generation for sequential HDL models under an observability-based code coverage metric.
IEEE Trans. Very Large Scale Integr. Syst., 2002
J. Circuits Syst. Comput., 2002
Binary Time Frame Expansion.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Runtime mechanisms for leakage current reduction in CMOS VLSI circuits<sup>1, 2</sup>.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
EZ Encoding: A Class of Irredundant Low Power Codes for Data Address and Multiplexed Address Buses.
Proceedings of the 2002 Design, 2002
2001
OCCOM-efficient computation of observability-based code coveragemetrics for functional verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Functional vector generation for HDL models using linearprogramming and Boolean satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
1999
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage.
Proceedings of the 36th Conference on Design Automation, 1999
1998
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification.
Proceedings of the 35th Conference on Design Automation, 1998
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.
Proceedings of the 35th Conference on Design Automation, 1998