Farrukh Hijaz

According to our database, Farrukh Hijaz authored at least 14 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Alternating Blind Identification of Power Sources for Mobile SoCs.

Sofiane Chetoui, Michael Chen, Abhinav Golas, Farrukh Hijaz, Adel Belouchrani, Sherief Reda

Proceedings of the ICPE '22: ACM/SPEC International Conference on Performance Engineering, Bejing, China, April 9, 2022

ARBench: Augmented Reality Benchmark For Mobile Devices.

Sofiane Chetoui, Rahul Shahi, Seif Abdelaziz, Abhinav Golas, Farrukh Hijaz, Sherief Reda

Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2017

Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging.

Halit Dogan, Farrukh Hijaz, Masab Ahmad, Brian Kahne, Peter Wilson, Omer Khan

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016

Locality-aware data replication in the last-level cache for large scale multicores.

Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan

J. Supercomput., 2016

LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.

Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan

ACM Trans. Archit. Code Optim., 2016

2015

M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors.

Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk

IACR Cryptol. ePrint Arch., 2015

Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication.

Farrukh Hijaz, Brian Kahne, Peter Wilson, Omer Khan

Proceedings of the 10th IEEE International Conference on Networking, 2015

Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads.

Masab Ahmad, Syed Kamran Haider, Farrukh Hijaz, Marten van Dijk, Omer Khan

Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.

Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan

Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

2014

NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages.

Farrukh Hijaz, Omer Khan

ACM Trans. Archit. Code Optim., 2014

2013

Towards efficient dynamic data placement in NoC-based multicores.

Qingchuan Shi, Farrukh Hijaz, Omer Khan

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages.

Farrukh Hijaz, Qingchuan Shi, Omer Khan

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores.

Farrukh Hijaz, Qingchuan Shi, Omer Khan

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011

ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores.

Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas

Proceedings of the IEEE 29th International Conference on Computer Design, 2011