Farnoud Farahmand
According to our database1,
Farnoud Farahmand
authored at least 26 papers
between 2015 and 2021.
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Bibliography
2021
Side-channel Resistant Implementations of a Novel Lightweight Authenticated Cipher with Application to Hardware Security.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
FPGA Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process: Methodology, Metrics, Tools, and Results.
IACR Cryptol. ePrint Arch., 2020
Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches.
IACR Cryptol. ePrint Arch., 2020
2019
A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography.
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
CoRR, 2019
Full hardware implementation of the Post-Quantum Public-Key Cryptography Scheme Round5.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019
Proceedings of the 22nd International Symposium on Research in Attacks, 2019
Evaluating the Potential for Hardware Acceleration of Four NTRU-Based Key Encapsulation Mechanisms Using Software/Hardware Codesign.
Proceedings of the Post-Quantum Cryptography - 10th International Conference, 2019
Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign.
Proceedings of the International Conference on Field-Programmable Technology, 2019
Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Software/Hardware Codesign of the Post Quantum Cryptography Algorithm NTRUEncrypt Using High-Level Synthesis and Register-Transfer Level Design Methodologies.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
2018
IACR Cryptol. ePrint Arch., 2018
Comparison of Cost of Protection against Differential Power Analysis of Selected Authenticated Ciphers.
Cryptogr., 2018
Proceedings of the International Conference on Field-Programmable Technology, 2018
Proceedings of the 2018 Workshop on Attacks and Solutions in Hardware Security, 2018
2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Comparison of hardware and software implementations of selected lightweight block ciphers.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
2016
A Zynq-based testbed for the experimental benchmarking of algorithms competing in cryptographic contests.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Big biomedical image processing hardware acceleration: A case study for K-means and image filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015