Farnaz Toussi

Affiliations:
  • IBM, Rochester, MN, USA


According to our database1, Farnaz Toussi authored at least 11 papers between 1994 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2019
NetStorage: A synchronized trace-driven replayer for network-storage system evaluation.
Perform. Evaluation, 2019

2017
TraceRAR: An I/O Performance Evaluation Tool for Replaying, Analyzing, and Regenerating Traces.
Proceedings of the 2017 International Conference on Networking, Architecture, and Storage, 2017

2014
Architecture and Performance of the Hardware Accelerators in IBM's PowerEN Processor.
ACM Trans. Parallel Comput., 2014

2012
Hardware acceleration in the IBM PowerEN processor: architecture and performance.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2001
A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology.
IEEE J. Solid State Circuits, 2001

1999
SOI Implementation of a 64-Bit Adder.
Proceedings of the IEEE International Conference On Computer Design, 1999

1998
The Effect of using State-Based Priority Information in a Shared-Memory Multiprocessor Cache Replacement Policy.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1995
The Potential of Compile-Time Analysis to Adapt the Cache Coherence Enforcement Strategy to the Data Sharing Characteristics.
IEEE Trans. Parallel Distributed Syst., 1995

Write buffer design for cache-coherent shared-memory multiprocessors.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994
A Compiler-Assisted Scheme for Adaptive Cache Coherence Enforcement.
Proceedings of the Parallel Architectures and Compilation Techniques, 1994

An evaluation of a compiler optimization for improving the performance of a coherence directory.
Proceedings of the 8th international conference on Supercomputing, 1994


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