Farimah Farahmandi
Orcid: 0000-0003-1535-0938
According to our database1,
Farimah Farahmandi
authored at least 126 papers
between 2013 and 2025.
Collaborative distances:
Collaborative distances:
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Bibliography
2025
DL-SCADS: Deep Learning-Based Post-Silicon Side-Channel Analysis Using Decomposed Signal.
IACR Cryptol. ePrint Arch., 2025
SPY-PMU: Side-Channel Profiling of Your Performance Monitoring Unit to Leak Remote User Activity.
IACR Cryptol. ePrint Arch., 2025
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
IEEE Des. Test, August, 2024
IEEE Des. Test, August, 2024
IEEE Trans. Very Large Scale Integr. Syst., July, 2024
FLAT: Layout-Aware and Security Property-Assisted Timing Fault-Injection Attack Assessment.
IEEE Trans. Very Large Scale Integr. Syst., June, 2024
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
IEEE Trans. Very Large Scale Integr. Syst., February, 2024
ACM Trans. Design Autom. Electr. Syst., January, 2024
Exploring the Abyss? Unveiling Systems-on-Chip Hardware Vulnerabilities Beneath Software.
IEEE Trans. Inf. Forensics Secur., 2024
IEEE Trans. Inf. Forensics Secur., 2024
Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration.
IEEE Trans. Inf. Forensics Secur., 2024
IACR Cryptol. ePrint Arch., 2024
SoCureLLM: An LLM-driven Approach for Large-Scale System-on-Chip Security Verification and Policy Generation.
IACR Cryptol. ePrint Arch., 2024
IACR Cryptol. ePrint Arch., 2024
Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.
IEEE Access, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware Designs.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
SECT-HI: Enabling Secure Testing for Heterogeneous Integration to Prevent SiP Counterfeits.
Proceedings of the IEEE International Test Conference, 2024
HI-SST: Safeguarding SiP Authenticity Through Secure Split-Test in Heterogeneous Integration.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Towards Quantum-Resistant Security: Pre-Silicon Power Side-Channel Leakage Analysis of CRYSTALS-Kyber.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
SAP: Silicon Authentication Platform for System-on-Chip Supply Chain Vulnerabilities.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
TDM: Time and Distance Metric for Quantifying Information Leakage Vulnerabilities in SoCs.
Proceedings of the 42nd IEEE International Conference on Computer Design, 2024
Empowering Hardware Security with LLM: The Development of a Vulnerable Hardware Database.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Prioritizing Information Flow Violations: Generation of Ranked Security Assertions for Hardware Designs.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
DyFORA: Dynamic Firmware Obfuscation and Remote Attestation using Hardware Signatures.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
SeeMLess: Security Evaluation of Logic Locking using Machine Learning oriented Estimation.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
RL-TPG: Automated Pre-Silicon Security Verification through Reinforcement Learning-Based Test Pattern Generation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
FSMx-Ultra: Finite State Machine Extraction From Gate-Level Netlist for Security Assessment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations.
IEEE Des. Test, October, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology.
IEEE Des. Test, April, 2023
Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.
ACM J. Emerg. Technol. Comput. Syst., January, 2023
IACR Cryptol. ePrint Arch., 2023
ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction.
IACR Cryptol. ePrint Arch., 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
BitFREE: On Significant Speedup and Security Applications of FPGA Bitstream Format Reverse Engineering.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
ActiWate: Adaptive and Design-agnostic Active Watermarking for IP Ownership in Modern SoCs.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification.
IEEE Trans. Consumer Electron., 2022
SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance.
IACR Cryptol. ePrint Arch., 2022
Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications.
IACR Cryptol. ePrint Arch., 2022
PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions.
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
FSMx: Finite State Machine Extraction from Flattened Netlist With Application to Security.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
RTL-FSMx: Fast and Accurate Finite State Machine Extraction at the RTL for Security Applications.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference, 2022
LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
2021
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.
ACM Trans. Design Autom. Electr. Syst., 2021
IACR Cryptol. ePrint Arch., 2021
IACR Cryptol. ePrint Arch., 2021
SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the IEEE International Test Conference, 2021
Proceedings of the IEEE International Test Conference, 2021
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.
ACM Trans. Design Autom. Electr. Syst., 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE European Test Symposium, 2020
2019
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
IACR Cryptol. ePrint Arch., 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019
2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Scalable Hardware Trojan Activation by Interleaving Concrete Simulation and Symbolic Execution.
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Automated Debugging of Arithmetic Circuits Using Incremental Gröbner Basis Reduction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Exploiting transaction level models for observability-aware post-silicon test generation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction.
Microprocess. Microsystems, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
2014
Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
2013
Proceedings of the East-West Design & Test Symposium, 2013